IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
FEATURES:
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC162836
DESCRIPTION:
This 20-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. The device operates in the transparent mode when the latch-enable
(LE) input is low. When
LE
is high, the A data is latched if the clock (CLK)
input is held at a high or low logic level. If
LE
is high, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLK. When
OE
is high,
the outputs are in the high-impedance state.
The ALVC162836 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
Drive Features for ALVC162836:
– Light Balanced Output Drivers: ±12mA
– Minimal switching noise
APPLICATIONS:
•
SDRAM Modules
•
PC Motherboards
•
Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
1
CLK
56
LE
29
A
1
55
1
D
2
C
1
CLK
Y
1
TO 19 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
JULY 2001
DSC-4900/3
IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
Y
1
Y
2
GND
Y
3
Y
4
V
CC
Y
5
Y
6
Y
7
GND
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
GND
Y
14
Y
15
Y
16
V
CC
Y
17
Y
18
GND
Y
19
Y
20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
A
1
A
2
GND
A
3
A
4
V
CC
A
5
A
6
A
7
GND
A
8
A
9
A
10
A
11
A
12
A
13
GND
A
14
A
15
A
16
V
CC
A
17
A
18
GND
A
19
A
20
LE
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
– 0.5 to V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Min.
3.3
—
—
Typ.
5
7
7
Max. Unit
6
9
9
pF
pF
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Inputs
OE
H
L
L
L
L
L
L
LE
X
L
L
H
H
H
H
CLK
X
X
X
↑
↑
H
L
Ax
X
L
H
L
H
X
X
Outputs
Yx
Z
L
H
L
H
Y
0
Y
0
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
NC
c
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Active LOW)
Data Inputs
3-State Outputs
No Internal Connection
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑=
LOW-to-HIGH Transition
Y
0
= Output level before the indicated steady-state input conditions were
established.
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
V
CC
= 2.7V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
NEW16link
Unit
V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
3
IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
31
7
V
CC
= 3.3V ± 0.3V
Typical
36
11
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
H
t
H
t
SK
(o)
Parameter
Propagation Delay
Ax to Yx
Propagation Delay
LE
to Yx
Propagation Delay
CLK to Yx
Output Enable Time
OE
to Yx
Output Disable Time
OE
to Yx
Pulse Duration,
LE
LOW
Pulse Duration, CLK HIGH or LOW
Setup Time, data before CLK↑
Setup Time, data before
LE
↑,
CLK HIGH
Setup Time, data before
LE
↑,
CLK LOW
Hold Time, data after CLK↑
Hold Time, data after
LE
↑,
CLK HIGH or LOW
Output Skew
(2)
Min
.
150
1
1.1
1
1.1
1
3.3
3.3
1.4
1.2
1.4
0.7
1.1
—
Max.
—
4.4
5.8
5.2
6.4
4.7
—
—
—
—
—
—
—
—
V
CC
= 2.7V
Min
.
150
—
—
—
—
—
3.3
3.3
1.7
1.6
1.5
0.7
1.1
—
Max.
—
4.6
6.1
5.5
6.5
5.2
—
—
—
—
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min
.
150
1.2
1.4
1.9
1.2
1.7
3.3
3.3
1.5
1.3
1.2
0.7
1.1
—
Max.
—
4
5.1
4.5
5.5
5.1
—
—
—
—
—
—
—
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, C
L
= 5pF
V
CC
= 3.3V ± 0.15V
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CLK to Yx
Min.
1.9
Max.
4.5
Unit
ns
4
IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PH AS E
IN PU T TR AN SITION
t
PLH
O U TPU T
t
PLH
O PPOS ITE PH ASE
IN PU T TR AN SITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
G enerator
(1, 2)
ENABLE AND DISABLE TIMES
EN ABLE
C O N TR O L
IN PU T
t
PZL
O U TPU T
SW ITCH
N O R M ALLY
CLO SE D
LO W
t
PZH
O U TPU T
SW ITCH
N O R M ALLY
OP EN
H IGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
D ISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALVC Link
V
LOAD
O pen
GND
V
IN
D .U .T.
V
OUT
R
T
500
Ω
C
L
DEFINITIONS:
ALVC Link
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
D ATA
IN PU T
TIM IN G
IN PU T
ASYN C H RO N OU S
C O N TR O L
SYN C H RO N OU S
C O N TR O L
t
R EM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
GND
Open
NEW16link
t
SU
t
H
OUTPUT SKEW -
IN PU T
TSK
(x)
V
IH
V
T
0V
V
OH
t
PHL1
t
PLH1
PULSE WIDTH
LO W -H IG H -LO W
PU LSE
t
W
H IGH -LO W -H IG H
PU LSE
V
T
ALVC Link
O U TPU T 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
O U TPU T 2
t
PLH2
t
PHL2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
P HL1
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank..
ALVC Link
5
stm32/stm8
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