FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12607-2E
8-bit Proprietary Microcontrollers
CMOS
F
2
MC-8FX MB95150H Series
MB95F156H/F156T/FV100B-103
■
DESCRIPTION
The MB95150H series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
■
FEATURE
•
F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
•
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
•
Timer
• 8/16-bit compound timer
×
2 channels
• 8/16-bit PPG
×
2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB95150H Series
(Continued)
•
LIN-UART
• Full duplex double buffer
• Clock asynchronous or clock synchronous serial data transfer capable
•
UART/SIO
• Full duplex double buffer
• Clock asynchronous or clock synchronous serial data transfer capable
•
External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
•
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
•
LCD controller (LCDC)
• 16 SEG
×
4 COM (Max 64 pixels)
• With blinking function
•
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
•
I/O port: Max 39
• General-purpose I/O ports (CMOS) : 39 ports
2
MB95150H Series
■
PRODUCT LINEUP
Part number*
1
MB95F156H
Parameter
Type
ROM capacity
RAM capacity
Reset output
Option*
2
Clock system
Low voltage detection
reset
No
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
General-purpose I/O port (CMOS)
Reset generated cycle
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz
Flash memory product
32 Kbytes
1 Kbyte
Yes
Dual clock
Yes
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 0.1
µs
(at machine clock frequency 10 MHz)
: 0.9
µs
(at machine clock frequency 10 MHz)
: 39 ports
MB95F156T
CPU functions
Ports (Max 39 ports)
Timebase timer
Watchdog timer
Wild register
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
: Min 105 ms
: Min 250 ms
Capable of replacing 3 bytes of ROM data
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
Transfer rate : 2400 bps to 1250000 bps (at machine clock 10 MHz)
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Capable of serial data transfer synchronous or asynchronous to clock signal.
LIN functions available as the LIN master or LIN slave.
Peripheral functions
UART/SIO
LIN-UART
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(8 channels)
COM output
: 4 (Max)
SEG output
: 16 (Max)
LCD drive power supply (bias) pin
:4
16 SEG
×
4 COM
: 64 pixels can be displayed.
Duty LCD mode
With blinking function
Built-in division resistance for LCD drive
(Continued)
LCD controller
(LCDC)
3
MB95150H Series
(Continued)
Part number*
1
MB95F156H
Parameter
Each channel of the timer can be used as “8-bit timer
×
2 channels” or “16-bit timer
×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
Count clock : 7 internal clocks and external clock can be selected.
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
Each channel of the PPG can be used as
“
8-bit PPG
×
2 channels
”
or
“
16-bit PPG
×
1 channel
”
.
Counter operating clock : Eight selectable clock sources
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Sleep, stop, watch, and timebase timer
MB95F156T
8/16-bit compound
timer (2 channels)
Peripheral functions
16-bit PPG
8/16-bit PPG
(2 channels)
Watch counter
Watch prescaler
External interrupt
(8 channels)
Standby mode
*1 : MASK ROM products are currently under consideration.
*2 : For details of option, refer to “■ MASK OPTION”.
Note : Part number of evaluation device in MB95150H series is MB95FV100B-103. When using it, the MCU board
(MB2146-303) is required.
■
OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
(2
14
−2)
/F
CH
Remarks
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■
PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
FPT-48P-M26
FPT-52P-M01
BGA-224P-M08
: Available
: Unavailable
4
MB95F156H
MB95F156T
MB95FV100B-103
MB95150H Series
■
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
•
Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95150H series corresponding products series but
also those of other products to support software development for multiple series and models of the F
2
MC-8FX
family. The I/O addresses for peripheral resources not used by the MB95150H series are therefore access-
barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be
unused to operate, resulting in unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Note that the values read from barred addresses are different between the Evaluation product and the Flash
memory products. Therefore, the data must not be used for software processing.
The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access
to these bits does not cause hardware malfunctions. The Evaluation and Flash memory products are designed
to behave completely the same way in terms of hardware and software.
•
Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory products, carefully
check the difference in the amount of memory from the model to be actually used when developing software.
For details of memory space, refer to “■ CPU CORE”.
•
Current Consumption
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
•
Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSIONS”.
•
Operating voltage
The operating voltage is different among the Evaluation and Flash memory products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
5
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