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IDT7052L20

产品描述Four-Port SRAM, 2KX8, 20ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108
产品类别存储    存储   
文件大小123KB,共11页
制造商IDT (Integrated Device Technology)
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IDT7052L20概述

Four-Port SRAM, 2KX8, 20ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108

IDT7052L20规格参数

参数名称属性值
厂商名称IDT (Integrated Device Technology)
零件包装代码PGA
包装说明1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108
针数108
Reach Compliance Codecompliant
ECCN代码EAR99
最长访问时间20 ns
JESD-30 代码S-CPGA-P108
JESD-609代码e0
长度30.48 mm
内存密度16384 bit
内存集成电路类型FOUR-PORT SRAM
内存宽度8
功能数量1
端子数量108
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织2KX8
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码PGA
封装形状SQUARE
封装形式GRID ARRAY
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度5.207 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层TIN LEAD
端子形式PIN/PEG
端子节距2.54 mm
端子位置PERPENDICULAR
宽度30.48 mm

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HIGH-SPEED
2K x 8 FourPort
TM
STATIC RAM
Features
IDT7052S/L
High-speed access
– Commercial: 20/25/35ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35ns (max.)
Low-power operation
– IDT7052S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7052L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
P1, P2, P3, P4
Versatile control for write-inhibit: separate
BUSY
input to
control write-inhibit for each of the four ports
Battery backup operation—2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 120 pin and 132 pin Thin Quad Flatpacks and
108 pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7052 is also designed to be used in systems where on-chip
Functional Block Diagram
R/W
P1
CE
P1
OE
P1
I/O
0P1
-I/O
7P1
BUSY
P1
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
COLUMN
I/O
COLUMN
I/O
R/W
P4
CE
P4
OE
P4
I/O
0P4
-I/O
7P4
BUSY
P4
A
0P1
- A
10P1
A
0P4
- A
10P4
MEMORY
ARRAY
A
0P2
- A
10P2
BUSY
P2
I/O
0P2
-I/O
7P2
OE
P2
CE
P2
R/W
P2
A
0P3
- A
10P3
BUSY
P3
COLUMN
I/O
COLUMN
I/O
I/O
0P3
-I/O
7P3
OE
P3
CE
P3
R/W
P3
2674 drw 01
NOVEMBER 2001
1
©2001 Integrated Device Technology, Inc.
DSC 2674/11
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