The documentation and process conversion measures
necessary to comply with this document shall be
completed by 2 January 2014.
INCH-POUND
MIL-PRF-19500/368M
2 October 2013
SUPERSEDING
MIL-PRF-19500/368L
20 November 2010
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, LOW-POWER
TYPES: 2N3439, 2N3439L, 2N3439UA, 2N3439U4, 2N3440, 2N3440L, 2N3440UA, AND
2N3440U4, JAN, JANTX, JANTXV, JANS, JANHCB, JANKCB, JANHCC, JANKCC JANSM,
JANSD, JANSP, JANSL, JANSR, JANSF, JANSG, JANSH, JANKCBM, JANKCBD,
JANKCBP, JANKCBL, JANKCBR, JANKCBF, JANKCBG, AND JANKCBH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, low-power, high voltage
transistors. Four levels of product assurance are provided for each encapsulated device types as specified in
MIL-PRF-19500, and two levels of product assurance for each unencapsulated device type die. RHA level
designators “M”, “D”, “P“, “L”, “R”, “F”, “G”, and “H” are appended to the device prefix to identify devices, which have
passed RHA requirements.
1.2 Physical dimensions. See figure 1 (similar to TO-5 and TO-39), figure 2 (JANHCB and JANKCB
(B versions)), figure 3 (2N3439UA and 2N3440UA surface mount versions), figure 4 (2N3439U4 and 2N3440U4
versions), and figure 5 (JANHCC and JANKCC (C versions)).
1.3 Maximum ratings. Unless otherwise specified, T
A
= +25°C.
Types
P
T
(1)
T
A
=
+25°C
W
2N3439
2N3439L
2N3439UA
2N3439U4
2N3440
2N3440L
2N3440UA
2N3440U4
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
P
T
(2)
T
C
=
+25°C
W
5.0
5.0
N/A
5
5.0
5.0
N/A
5
P
T
(2)
T
SP
=
+25°C
W
N/A
N/A
2.0
N/A
N/A
N/A
2.0
N/A
°C/W
175
175
175
175
175
175
175
175
°C/W
30
30
N/A
8
30
30
N/A
8
°C/W
N/A
N/A
70
N/A
N/A
N/A
70
N/A
V dc
450
450
450
450
300
300
300
300
V dc
7
7
7
7
7
7
7
7
V dc
350
350
350
350
250
250
250
250
A dc
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
R
θJA
(3)
R
θJC
(3)
R
θJSP
(3)
V
CBO
V
EBO
V
CEO
I
C
T
STG
and
T
J
°C
-65 to
+200
(1) For derating, see figure 6.
(2) For derating, see figures 7, 8, and 9.
(3) For thermal impedance curves see figures 10, 11, 12, and 13.
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since
contact information can change, you may want to verify the currency of this address information using the
ASSIST Online database at
https://assist.dla.mil
.
AMSC N/A
FSC 5961
MIL-PRF-19500/368L
1.4 Primary electrical characteristics. Unless otherwise specified T
A
= +25°C.
h
FE2
(1)
V
CE
= 10 V dc
I
C
= 2 mA dc
h
FE1
(1)
V
CE
= 10 V dc
I
C
= 20 mA dc
|h
fe
|
V
CE
= 10 V dc
I
C
= 10 mA dc
f = 5 MHz
C
obo
V
CB
= 10 V dc
I
E
= 0
100 kHz
≤
f
≤
1 MHz
pF
V
BE(sat)
(1)
I
C
= 50 mA dc
I
B
= 4 mA dc
V
CE(sat)
I
C
= 50 mA dc
I
B
= 4 mA dc
V dc
1.3
V dc
0.5
Min
Max
30
40
160
3
15
10
(1) Pulsed, (see 4.5.1).
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This
section does not include documents cited in other sections of this specification or recommended for additional
information or as examples. While every effort has been made to ensure the completeness of this list, document
users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this
specification, whether or not they are listed.
2.2 Government documents.
2.2.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a
part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are
those cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONS
MIL-PRF-19500
-
Semiconductor Devices, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-750
-
Test Methods for Semiconductor Devices.
* (Copies of these documents are available online at
http://quicksearch.dla.mil
or
https://assist.dla.mil
or from the
Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.3 Order of precedence. Unless otherwise noted herein or in the contract, in the event of a conflict between the
text of this document and the references cited herein, the text of this document takes precedence. Nothing in this
document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.
2
MIL-PRF-19500/368M
Symbol
CD
CH
HD
LC
LD
LL
LU
L1
L2
P
Q
TL
TW
r
α
Dimensions
Inches
Millimeters
Min
Max
Min
Max
.305
.335
7.75
8.51
.240
.260
6.10
6.60
.335
.370
8.51
9.40
.200 TP
5.08 TP
.016
.019
0.41
0.48
See note 14
.016
.019
0.41
0.48
.050
1.27
.250
6.35
.100
2.54
.030
0.76
.029
.045
0.74
1.14
.028
.034
0.71
0.86
.010
0.25
45° TP
45° TP
Note
6
7
8,9
8,9
8,9
8,9
7
5
3,4
3
10
7
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Beyond r (radius) maximum, TW shall be held for a minimum length of .011 (0.28 mm).
4. Dimension TL measured from maximum HD.
5. Body contour optional within zone defined by HD, CD, and Q.
6. CD shall not vary more than .010 inch (0.25 mm) in zone P. This zone is controlled for automatic handling.
7. Leads at gauge plane .054 +.001 -.000 inch (1.37 +0.03 -0.00 mm) below seating plane shall be within .007
inch (0.18 mm) radius of true position (TP) at maximum material condition (MMC) relative to tab at MMC.
The device may be measured by direct methods or by gauging procedure.
8. Dimension LU applies between L1 and L2. Dimension LD applies between L2 and LL minimum. Diameter is
uncontrolled in and beyond LL minimum.
9. All three leads.
10. The collector shall be internally connected to the case.
11. Dimension r (radius) applies to both inside corners of tab.
12. In accordance with ASME Y14.5M, diameters are equivalent to
Φx
symbology.
13. Lead 1 = emitter, lead 2 = base, lead 3 = collector.
14. For transistor types 2N3439L and 2N3440L (T0-5), dimension LL = 1.5 inches (38.10 mm) min. and 1.75
inches (44.45 mm) max. For transistor types 2N3439 and 2N3440 (T0-39), dimension LL = .5 inch (12.70
mm) min. and .750 inch (19.05 mm) max.
FIGURE 1. Physical dimensions (similar to TO-5 and TO-39).
3
MIL-PRF-19500/368M
E
B
1.
2.
3.
4.
Chip size.................................
Chip thickness........................
Top metal................................
Back metal...............................
5. Backside.................................
6. Bonding pad...........................
.049 x .057 inch
±.002
inch (1.24 mm x 1.45 mm
±0.05
mm).
.010
±
.0015 inch nominal (0.254 mm
±0.038
mm).
Aluminum 15,000Å minimum, 18,000Å nominal
A. Al/Ti/Ni/Ag 12kÅ/3kÅ/7kÅ/7kÅminimum,15kÅ/ 5kÅ/10kÅ/10kÅ nominal.
B. Gold 3,500Å minimum, 5,000Å nominal.
Collector.
B = .005 x .008 inch (0.127 mm x 0.203 mm).
E = .010 x .007 inch (0.254 mm x 0.178 mm).
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. In accordance with ASME Y14.5M, diameters are equivalent to
φx
symbology.
FIGURE 2. Physical dimensions JANHCB and JANKCB (die) B versions.
4
MIL-PRF-19500/368M
UA
Symbol
BL
BL2
BW
BW2
CH
L3
LH
LL1
LL2
LS
LW
LW2
Pin no.
Transistor
Dimensions
Inches
Millimeters
Min
Max
Min
Max
.215
.225
5.46
5.71
.225
5.71
.145
.155
3.68
3.93
.155
3.93
.061
.075
1.55
1.90
.003
0.08
.029
.042
0.74
1.07
.032
.048
0.81
1.22
.072
.088
1.83
2.23
.045
.055
1.14
1.39
.022
.028
0.56
0.71
.006
.022
0.15
0.56
1
Collector
2
Emitter
3
Base
Note
3
5
5
4
N/C
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Dimension "CH" controls the overall package thickness. When a window lid is used, dimension "CH" must
increase by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).
4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the
drawing.
* 5. Dimensions " LW2" minimum and "L3" minimum and the appropriate castellation length define an unobstructed
three-dimensional space traversing all of the ceramic layers in which a castellation was designed.
(Castellations are required on bottom two layers, optional on top ceramic layer.) Dimension " LW2" maximum
define the maximum width and depth of the castellation at any point on its surface.
Measurement of these dimensions may be made prior to solder dipping.
6. The coplanarity deviation of all terminal contact points, as defined by the device seating plane, shall not exceed
.006 inch (0.15mm) for solder dipped leadless chip carriers.
7. In accordance with ASME Y14.5M, diameters are equivalent to
φx
symbology.
* FIGURE 3. Physical dimensions, surface mount (2N3439UA, 2N3440UA) version.
5
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