512K x 8-bit CMOS, 5.0 Volt-only, Sector Erase Flash Memory
HY29F040 Series
KEY FEATURES
•
5.0 V ± 10% Read, Program, and Erase
- Minimizes system-level power requirements
•
High performance
-
90 ns access time
•
Low Power Consumption
- 20 mA typical active read current
- 30 mA typical program/erase current
•
Compatible with the JEDEC Standard for
Single-Voltage Flash Memories
- Uses software commands, pinouts, and
packages following the industry standards
for single power supply Flash memories
- Superior inadvertent write protection
•
Flexible Sector Architecture
- Eight equal size sectors of 64K bytes each
- Any combination of sectors can be erased
concurrently
- Supports full chip erase
•
Sector Protection
- Any sector may be locked to prevent any
program or erase operation within that sector
•
Erase Suspend/Resume
- Suspends a sector erase operation to allow
data to be read from, or programmed into,
any sector not being erased
- The erase operation can then be resumed
•
Internal Erase Algorithm
- Automatically erases a sector, any combination
of sectors, or the entire chip
•
Internal Programming Algorithm
- Automatically programs and verifies data at a
specified address
•
Minimum 100,000 Program/Erase Cycles
•
PLCC, PDIP and TSOP Packages
DESCRIPTION
The HY29F040 is a 4 Megabit, 5.0 volt-only, CMOS
Flash memory device organized as 524,288
(512 K) bytes of 8 bits each. The Flash memory
array is organized into eight uniform-sized sec-
tors of 64 Kbytes each. The device is offered
with access times of 90, 120 and 150 ns and is
provided in standard 32-pin PDIP, PLCC and
TSOP packages. It is designed to be pro-
grammed and erased in-system with a 5.0 volt
power-supply and can also be reprogrammed
in standard PROM programmers.
The HY29F040 has separate chip enable (/CE),
write enable (/WE) and output enable (/OE) con-
trols. Hyundai Flash memory devices reliably
store memory data even after 100,000 program/
erase cycles.
The device is entirely pin and command set
compatible with the JEDEC standard for 4 Mega-
bit Flash memory devices. Commands are writ-
ten to an internal command register using stan-
dard microprocessor write timings. Register
contents serve as inputs to an internal state-
machine which controls the erase and pro-
gramming circuitry. Write cycles also internally
latch addresses and data needed for the pro-
gramming and erase operations.
The HY29F040 is programmed by invoking the
program command sequence. This starts the
internal byte programming algorithm that auto-
matically times the program pulse width and
verifies the proper cell margin. An erase opera-
tion is performed likewise, by invoking the sec-
tor erase or chip erase command sequence.
This starts the internal erasing algorithm that
automatically preprograms the sector (if it is not
already programmed), times the erase pulse
width and verifies the proper cell margin. Sec-
tors of the HY29F040 Flash memory array are
electrically erased via Fowler-Nordheim tunnel-
ing. Bytes are programmed one byte at a time
using a hot electron injection mechanism.
The HY29F040 features a flexible sector erase
architecture. The device memory array is divided
into eight sectors of 64K bytes each. The sec-
tors can be erased individually or in groups with-
out affecting the data in other sectors. The mul-
tiple sector erase and full chip erase capabili-
ties provide flexibility in altering the data in the
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licences are implied.
Rev.04: April 1998
Hyundai Semiconductor
device. To protect data in the device from acci-
dental program and erase, the device has a
sector protect function which hardware write
protects selected sectors. The sector protect and
sector unprotect features can be enabled in a
PROM programmer.
The HY29F040 requires only a single five-volt
BLOCK DIAGRAM
power supply for read, program and erase
operations. Internally generated and regulated
voltages are provided for the program and erase
operations. A low V
CC
detector inhibits write op-
erations during power transitions. End of pro-
gram or erase is detected by /Data Polling of
DQ7 or by the Toggle Bit feature on DQ6. Once
the program or erase cycle is successfully
completed, the device internally resets to the
Read mode.
DQ[7:0]
STATE
CONTROL
DQ[7:0]
/WE
/CE
/OE
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
I/O BUFFERS
ELECTRONIC
ID
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
ADDRESS LATCH
Y-DECODER
Y-GATING
4 Mbit FLASH
MEMORY
ARRAY
(8 x 512 Kbit
Sectors)
V
SS
V
CC
A[18:0]
V
CC
DETECTOR
TIMER
X-DECODER
PIN DESCRIPTIONS
Pin Name
A[18:0]
DQ[7:0]
/CE
/OE
/WE
V
SS
V
CC
2
LOGIC SYMBOL
19
A[18:0]
DQ[7:0]
8
Pin Function
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Device Ground
Device Power Supply
/CE
/OE
/WE
HY29F040
Table 3. Sector Addresses
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
Address Range
00000H - 0FFFFH
10000H - 1FFFFH
20000H - 2FFFFH
30000H - 3FFFFH
40000H - 4FFFFH
50000H - 5FFFFH
60000H - 6FFFFH
70000H - 7FFFFH
current until the programming or erase operation is
completed.
Read Mode
The HY29F040 has three control functions
which must be satisfied in order to obtain data
at the DQ[7:0] outputs. /CE is the power control
and is used for device selection. /OE is the out-
put control and is used to gate data to the out-
puts when a device is selected. As shown in
Table 1, /WE should be held at V
IH
, except in
Write mode and Enable Sector Protect/Unprotect
modes.
Address access time (t
ACC
) is equal to the delay
from stable addresses to valid output data. The
chip enable access time (t
CE
) is the delay from
stable addresses and stable /CE to valid data
at the output pins. The output enable access
time is the delay from the falling edge of /OE to
valid data at the output pins (assuming the ad-
dresses have been stable for at least t
ACC
- t
OE
).
Output Disable Mode
With the /OE input at a logic High level (V
IH
), out-
puts from the device are disabled and the DQ[7:
0] pins are placed in a high impedance state.
Note, as shown in Table 1, that Write opera-
tions are possible while in this state if /WE is
brought Low.
Program and Erase Modes
Device programming and erase are accom-
plished via the command register. The contents
of the register serve as inputs to the internal
state machine. Outputs from the state machine
dictate the function of the device. Commands
are detailed in the Command Definitions sec-
tion of this document.
The command register itself does not occupy
any addressable memory locations. The regis-
ter is a latch used to store the commands along
with the address and data information needed
to execute a particular command. The com-
mand register is written by bringing /WE to V
IL
,
while /CE is at V
IL
and /OE is at V
IH
. Addresses
are latched on the falling edge of /WE or /CE,
whichever happens later, while data is latched
on the rising edge of /WE or /CE, whichever
happens first. Standard microprocessor write
timings are used. Refer to the AC Characteris-
5
Standby Mode
The HY29F040 has two standby modes: a
CMOS standby mode (/CE input held at V
CC
± 0.
5V), when current consumed is typically less
than 60
µA;
and a TTL standby mode (/CE is
held at V
IH
) when the typical current required is
reduced to 300
µA.
In standby mode, outputs
are in a high impedance state, independent of
the /OE input.
If the device is deselected during programming
or erase, the device will continue to draw active
HY29F040
FPGA/CPLD
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