HB526R864ESN-10H/10/12
4,194,304-word
×
64-bit (Non Parity)× 2-bank Synchronous
Dynamic RAM Module
ADE-203-671A (Z)
Rev. 1.1
Feb. 20, 1997
Description
The HB526R864ESN belongs to 8 byte DIMM (Dual In-line Memory Module) family, and has been
developed a as optimized main memory solution for 8 byte processor applications. The HB526R864ESN is
a 4M
×
64
×
2 banks Synchronous Dynamic RAM module, mounted 32 pieces of 16-Mbit SDRAM
(HM5216405TB) sealed in TCP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD).
An outline of the HB526R864ESN is 168-pin socket type package (dual lead out). Therefore, the
HB526R864ESN makes high density mounting possible without surface mount technology. The
HB526R864ESN provides common data inputs and outputs. Decoupling capacitors are mounted beside
each TCP on the module board.
Features
•
168-pin socket type package (dual lead out)
Lead pitch : 1.27 mm
•
3.3 V (
±0.3
V) power supply
•
Clock frequency : 100 MHz / 83 MHz
•
JEDEC standard outline unbuffered 8-byte DIMM
•
LVTTL interface
•
Data bus width:
×
64 (non parity)bit
•
Single pulsed
RAS
•
2 Banks can operate simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8/full page
•
Programmable burst sequence
Sequential/interleave
•
Full page burst length capability
Sequential burst
Burst stop capability
•
Programmable
CAS
latency: 1/2/3
•
4096 refresh cycles: 64 ms
HB526R864ESN-10H/10/12
•
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
HB526R864ESN-10H
HB526R864ESN-10
HB526R864ESN-12
Frequency
100 MHz
100 MHz
83 MHz
Package
Contact pad
168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin name
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Pin name
V
SS
NC
S2
DQMB2
DQMB3
NC
V
DD
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
Pin name
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Pin name
V
SS
CKE0
S3
DQMB6
DQMB7
NC
V
DD
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
2
HB526R864ESN-10H/10/12
Pin Arrangement
(cont)
Pin No.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin name
V
DD
DQ14
DQ15
NC
NC
V
SS
NC
NC
V
DD
WE
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
A6
A8
A10
NC
V
DD
V
DD
CK0
Pin No.
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin name
DQ20
NC
NC
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC
SDA
SCL
V
DD
Pin No.
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin name
V
DD
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
DD
CAS
DQMB4
DQMB5
S1
RAS
V
SS
A1
A3
A5
A7
A9
A11
NC
V
DD
CK1
NC
Pin No.
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin name
DQ52
NC
NC
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
3
HB526R864ESN-10H/10/12
Pin Description
Pin name
A0 to A11
Function
Address input
Row address
Column address
Bank select address
DQ0 to DQ63
S0
to
S3
(CS0 to
CS3)
RAS
CAS
WE
DQMB0 to DQMB7
(DQM0 to DQM7)
CK0 to CK3
(CLK0 to CLK3)
CKE0/CKE1
SDA
SCL
SA0 to SA2
V
DD
V
SS
NC
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Serial address input
Power supply
Ground
No connection
A0 to A10
A0 to A9
A11
4
HB526R864ESN-10H/10/12
Serial PD Matrix
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes utilized by module
manufacturer
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Notes
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
None
Normal
(15.625
µs)
Self refresh
CL = 3
21
256byte
SDRAM
11
10
2
64
0 (+)
3.3 V
CL = 3
Total number bytes in serial PD device 0
Memory type
Number of row addresses
Number of column addresses
Number of DIMM banks
Module data width
Module data width(continued)
0
0
0
0
0
0
Module supply voltage/interface levels 0
System clock cycle time
10 ns
12 ns
1
1
1
1
0
1
10
Access time from clock
8 ns
9.5 ns
11
12
SDRAM DIMM configuration type
Refresh rate/type
13
14
15
SDRAM module attributes
SDRAM device attributes: General
SDRAM device attributes:
minimum clock delay, back-to-back
random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
CAS
latency
SDRAM device attributes:
CS
latency
SDRAM device attributes:
WE
latency
0: Serial data, “driven Low”
1: Serial data, “driven High”
Serial-PD Data is not protected.
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
16
17
18
19
20
Note:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1, 2, 4, 8,
full page
2
2, 3
0
0
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
