512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial Temperature Range.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.5
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
0.1. Replace Design Target to Preliminary.
0.2. Delete 12ns part but add 17ns part.
0.3. Relax D.C and A.C parameters and insert new parameter(Icc
1
)
with the test condition.
0.3.1. Insert Icc
1
parameter with the test condition as address is
increased with binary count.
0.3.2. Relax D.C and A.C parameters.
Previous spec.
Relaxed spec.
Items
(15/ - /20ns part)
(15/17/20ns part)
Icc
190/ - /180mA
220/215/210mA
t
CW
10/ - /12ns
12/13/14ns
t
AW
10/ - /12ns
12/13/14ns
t
WP
(OE=H)
10/ - /12ns
12/13/14ns
t
WP1
(OE=L)
12/ - /14ns
15/17/20ns
t
DW
7/ - /9ns
8/9/10ns
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Delete Icc1 parameter with the test condition.
1.3. Update D.C parameters.
Previous spec.
Updated spec.
Items
(15/17/20ns part)
(15/17/20ns part)
Icc
220/215/210mA
170/165/160mA
1.4. Add the test condition for V
OH1
with Vcc=5V±5% at 25°C
1.5. Add timing diagram to define t
WP
as
″(Timing
Wave Form of
Write Cycle(CS=Low fixed)″
2.1 Add extended and industrial temperature range parts.
Draft Data
Jun. 14th, 1996
Sep. 16th, 1996
Remark
Design Target
Preliminary
Rev. 1.0
Jun. 5th, 1997
Final
Rev. 2.0
Jun. 5th, 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 15,17,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 10mA(Max.)
Operating KM684002A - 15 : 170mA(Max.)
KM684002A - 17 : 165mA(Max.)
KM684002A - 20 : 160mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM684002AJ : 36-SOJ-400
CMOS SRAM
GENERAL DESCRIPTION
The KM684002A is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
KM684002A uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM684002A is packaged
in a 400mil 36-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
A
0
A
1
1
2
3
4
5
6
7
8
9
10
36 N.C
35 A
18
34 A
17
33 A
16
32 A
15
31 OE
30 I/O
8
ORDERING INFORMATION
KM684002A-15/17/20
KM684002AE-15/17/20
KM684002AI-15/17/20
Commercial Temp.
Extended Temp.
Industrial Temp.
A
2
A
3
A
4
CS
I/O
1
I/O
2
Vcc
SOJ
29 I/O
7
28 Vss
27 Vcc
26 I/O
6
25 I/O
5
24 A
14
23 A
13
22 A
12
21 A
11
20 A
10
19 N.C
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
Vss
I/O
3
11
I/O
4
12
WE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
5
A
6
13
14
15
16
17
18
Row Select
A
7
Memory Array
1024 Rows
512x8 Columns
A
8
A
9
I/O
1
~I/O
8
Data
Cont.
I/O Circuit
Column Select
PIN FUNCTION
Pin Name
A
0
- A
18
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
CLK
Gen.
A
10
A
12
A
11
A
14
A
13
A
15
A
16
A
17
A
18
WE
CS
OE
CS
WE
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
-2-
Rev 2.0
February 1998
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Extended
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-25 to 85
-40 to 85
Unit
V
V
W
°C
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
*
V
IL
(Min) = -2.0V a.c(Pulse Width
≤
10ns) for I
≤
20mA
**
V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
10ns) for I
≤
20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
15ns
17ns
20ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1*
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-100µA
Test Conditions
Min
-2
-2
-
-
-
-
-
-
2.4
-
Max
2
2
170
165
160
50
10
0.4
-
3.95
mA
mA
V
V
Unit
µA
µA
mA
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
* V
CC
=5.0V, Temp.=25°C
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* NOTE : Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-3-
Rev 2.0
February 1998
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
+5.0V
480Ω
D
OUT
255Ω
30pF*
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
480Ω
D
OUT
255Ω
5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM684002A-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
KM684002A-17
Min
17
-
-
-
3
0
0
0
3
0
-
Max
-
17
17
8
-
-
8
8
-
-
17
KM684002A-20
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
-4-
Rev 2.0
February 1998
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM684002A-15
Min
15
12
0
12
12
15
0
0
8
0
3
Max
-
-
-
-
-
-
-
7
-
-
-
KM684002A-17
Min
17
13
0
13
13
17
0
0
9
0
3
Max
-
-
-
-
-
-
-
8
-
-
-
KM684002A-20
Min
20
14
0
14
14
20
0
0
10
0
3
Max
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
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