HIGH-SPEED
8K x 16 TriPort
STATIC RAM
Features
High-speed access
– Industrial: 55ns (max.)
Low-power operation
– IDT70P5258ML and IDT70P525ML
Active: 54mW (typ.)
Standby: 7.2
µ
W (typ.)
– IDT70V525ML
Active: 450mW (typ.)
Standby: 250
µ
W (typ.)
◆
◆
IDT70P5258ML
IDT70P525ML
IDT70V525ML
◆
◆
◆
◆
◆
◆
TriPort architecture allows simultaneous access to the
memory from all three ports
Fully asynchronous operation from each of the three
ports: P1, P2, and P3
IDT70P5258 supports 3.0V and 1.8V I/O's
Available in 144-ball 0.5mm-pitch
fpBGA
Industrial temperature range (–40°C to +85°C)
Greeen parts available, see ordering information
Functional Block Diagram
PORT 2
Address
Decode
BE
0P1,
BE
1P1
R/
W
P1
OE
P1
A
0P2
- A
11P2
CE
P2
R/
W
P2
OE
P2
I/O
0P1
-I/O
15P1
PORT 1
I/O
Control
PORT 2
I/O
Control
I/O
0P2
-I/O
15P2
Memory
Array
A
0P1
- A
11P1
BE
0P1,
BE
1P1
PORT 3
I/O
Control
CE
P3
R/
W
P3
OE
P3
PORT 1
Address
Decode
PORT 3
Address
Decode
BE
0P1,
BE
1P1
I/O
0P3
-I/O
15P3
A
0P3
- A
11P3
R/
W
P1
OE
P1
INT
P1 - P2
INT
P1 - P3
Interrupt
Control
CE
P2,
CE
P3
R/W
P2,
R/W
P3
INT
P3 - P1
INT
P2 - P1
OE
P2,
OE
P3
,
5681 drw 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC 5681/5
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Description
The IDT70X525X is a high-speed 8K x 16 TriPort Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This TriPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT70X525X is also designed to be used in systems where on-
chip hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to
externally arbitrated or withstand contention when more than one port
simultaneously accesses the same TriPort RAM location.
The IDT70X525X provides three independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. It is the user’s
responsibility to ensure data integrity when simultaneously accessing the
same memory location from mutiple ports. An automatic power down
feature, controlled by
BE
0
and
BE
1
on Port 1 and
CE
on Port 2 and on
Port 3, permits the on-chip circuitry of each port to enter a very low power
standby power mode.
The IDT70X525X is packaged in a 144-ball 0.5mm-pitch
fpBGA.
Pin Configurations
(1,2,3)
70(P/V)525XBZ
BZ-144
12/19/03
Top View
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A1
I/O
7P3
I/O
6P2
I/O
4P3
I/O
3P2
I/O
1P2
OE
P3
R/W
P2
B1
B2
B3
B4
B5
B6
B7
NC
B8
A
11P2
B9
A
9P2
B10
A
7P2
B11
A
6P2
B12
I/O
7P2
I/O
6P3
V
DD(1)
I/O
2P3
I/O
0P3
OE
P2
CE
P3
C1
C2
C3
C4
C5
C6
C7
NC
C8
A
10P3
C9
A
8P3
C10
A
6P3
C11
A
5P3
C12
I/O
9P2
D1
Vss
D2
I/O
5P2
I/O
2P2
I/O
0P2
R/W
P3
CE
P2
D3
D4
D5
D6
D7
A
11P3
A
10P2
D8
D9
A
8P2
D10
A
5P2
D11
A
4P3
D12
I/O
10P3
I/O
8P2
I/O
5P3
I/O
3P3
I/O
1P3
E1
E2
E3
E4
E5
V
DD
E6
V
DD(1)
E7
Vss
E8
A
9P3
E9
A
7P3
E10
A
4P2
E11
A
3P2
E12
I/O
11P3
I/O
11P2
I/O
8P3
I/O
4P2
F1
F2
F3
F4
V
DD
F5
Vss
F6
Vss
F7
Vss
F8
A
0P3
F9
A
3P3
F10
A
2P3
F11
A
2P2
F12
I/O
12P3
I/O
12P2
I/O
9P3
G1
G2
G3
V
DD(1)
G4
V
DD(1)
G5
Vss
G6
Vss
G7
Vss
G8
Vss
G9
V
DD
G10
A
1P3
G11
A
0P2
G12
I/O
15P2
I/O
13P3
I/O
10P2
I/O
13P2
H1
H2
H3
H4
Vss
H5
Vss
H6
Vss
H7
Vss
H8
Vss
H9
V
DD
H10
A
1P2
,
V
DD(1)
H12
H11
I/O
15P3
I/O
14P3
I/O
14P2
J1
J2
J3
V
DD
J4
Vss
J5
Vss
J6
Vss
J7
Vss
J8
V
DD
J9
V
DD
INT
P3P1
INT
P2P1
J10
J11
J12
I/O
2P1
I/O
1P1
K1
K2
V
DD
K3
Vss
K4
Vss
K5
Vss
K6
Vss
K7
V
DD
K8
V
DD
K9
A
0P1
INT
P1P3
INT
P1P2
K10
K11
K12
I/O
3P1
I/O
0P1
I/O
4P1
L1
L2
L3
Vss
L4
V
DD
L5
Vss
L6
V
DD
L7
V
DD
L8
A
10P1
L9
A
3P1
L10
A
2P1
L11
A
1P1
L12
I/O
6P1
I/O
5P1
I/O
8P1
I/O
10P1
I/O
12P1
I/O
14P1
OE
P1
BE
0P1
M1
M2
M3
M4
M5
M6
M7
M8
NC
M9
A
9P1
M10
A
7P1
M11
A
4P1
M12
I/O
7P1
NOTES:
1. V
DDQ
for 70P5258.
V
DD
I/O
9P1
I/O
11P1
I/O
13P1
I/O
15P1
R/W
P1
BE
1P1
A
11P1
A
8P1
A
6P1
A
5P1
5681 drw 02
6.42
2
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Pin Configurations
(1,2)
Symbol
A
0P1
- A
11P1
A
0P2
- A
11P2
A
0P3
- A
11P3
I/O
0P1
- I/O
15P1
I/O
0P2
- I/O
15P2
I/O
0P3
- I/O
15P3
R/W
P1
R/W
P2
R/W
P3
CE
P2
CE
P3
OE
P1
OE
P2
OE
P3
BE
0P1
BE
1P1
INT
P1 - P2
INT
P1 - P3
INT
P2 - P1
INT
P3 - P1
V
DD
V
DDQ
V
SS
Pin Name
Address Lines - Port 1 (Input)
Address Lines - Port 2 (Input)
Address Lines - Port 3 (Input)
Data I/O - Port 1
Data I/O - Port 2
Data I/O - Port 3
Read/Write - Port 1 (Input)
Read/Write - Port 2 (Input)
Read/Write - Port 3 (Input)
Chip Enable - Port 2 (Input)
Chip Enable - Port 3 (Input)
Output Enable - Port 1 (Input)
Output Enable - Port 2 (Input)
Output Enable - Port 3 (Input)
Bank Enable 0 - Port 1 (Input)
Bank Enable 1 - Port 1 (Input)
Interrupt
P1 - P2
- Port 1 (Output)
Interrupt
P1 - P3
- Port 1 (Output)
Interrupt
P2 - P1
- Port 2 (Output)
Interrupt
P3 - P1
- Port 3 (Output)
Power (Input)
Port Power Supply (Input)
(3,4)
Ground (Input)
5681 tbl 01
NOTES:
1. All V
DD
pins must be connected to the power supply.
2. All V
SS
pins must be connected to the ground supply.
3. IDT70P5258 only.
4. For Port 2 and Port 3.
6.42
3
Capacitance
Symbol
C
IN
Parameter
Inp ut
Cap ac itanc e
Outp ut
Cap ac itanc e
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
(1)
Preliminary
Industrial Temperature Range
(T
A
= +25°C, f = 1.0MHz)
Port
Po rt 1
Po rt 2 & 3
Po rt 1
Po rt 2 & 3
Conditions
(2)
V
IN
= 3d V
V
IN
= 3d V
V
OUT
= 3d V
V
OUT
= 3d V
Max
18
9
20
11
Unit
pF
pF
pF
pF
C
OUT
5681 tb l 03
NOTES:
1. This parameter is determined by device characterization but is not production tested.
2. 3dV references the interpolated capacitance when the input and the output signals switch
from 0V to 3V or from 3V to 0V.
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Ambient Temperature
Device
70P525
70P5258
70V525
NOTE:
1. This is the parameter T
A
. This is the "instant on" case temperature.
V
SS
0V
0V
V
DD
1.8V
+
100mV
3.0V
+
300mV
5681 tbl 04
Ind us trial
-40°C to +85°C
6.42
4
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Absolute Maximum Ratings
(1)
Symbol
V
TERM
V
TERM
V
TERM
(2)
T
BIAS
(3)
T
STG
T
JN
I
OUT
(fo r 70V525)
I
OUT
(fo r 70P525
and 70P5258)
Rati ng
Sup p ly Vo ltag e o n V
DD
with Re s p e c t to GND
Sup p ly Vo ltag e o n V
DDQ
with Re s p e c t to GND
Te rminal Vo ltag e
with Re s p e c t to GND
Te mp e rature Und e r Bias
Sto rag e Te mp e rature
J unc tio n Te mp e ratue
DC Outp ut Curre nt
DC Outp ut Curre nt
I ndustri al
-0. 5 to +2. 9
-0. 5 to +3. 6
-0. 5 to V
DD
+ 0. 3
(4)
-55 to +125
-65 to +150
+150
50
20
Uni t
V
V
V
o
o
o
C
C
C
mA
mA
5681 tb l 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed V
DD
+ 10% for Port 1 or V
DDQ
+ 10% for Port 2 and Port 3 for more than
25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 10% (Port 1) or V
DDQ
+ 10% (Port 2 and Port 3).
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. V
DDQ
+ 0.3V for 70P5258.
Recommended DC Operating Conditions
Symbol
Device
70P5258
V
DD
70P525
70V525
70P5258
V
DDQ
70P525
70V525
V
SS
All
70P5258
Port 2 & 3
V
IH
70P525
70V525
70P5258
Port 2 & 3
V
IL
70P525
70V525
All
All
Input Low Voltage
-0.2
-0.2
____
____
Port
Parameter
Min.
1.7
Typ.
1.8
1.8
3
3
____
____
Max.
1.9
1.9
3.3
3.3
____
____
Unit
All
Supply Voltage
1.7
2.7
V
Port 2 & 3
N/A
N/A
All
Port 1
Input High Voltage
All
All
Port 1
Ground
I/O Supply Voltage
(1)
2.7
____
____
V
0
1.2
2
1.2
2
-0.2
-0.2
0
____
____
0
V
DD
+0.2
V
DDQ
+0.2
V
V
____
____
____
____
V
DD
+0.2
V
DD
+0.2
0.4
0.6
V
0.4
0.6
5681 tbl 02
NOTES:
1. The supply voltage for all ports on the IDT70P525 and IDT70V525 is supplied by V
DD
so there are no V
DDQ
pins
on these devices.
2. V
IL
>
-1.5V for pulse width less than 10ns.
3. V
TERM
must not exceed V
DD
+ 10% for Port 1 or V
DDQ
+ 10% for Port 2 and Port 3.
6.42
5
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