SDC-36016
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has...
®
FOUR-CHANNEL S/D-R/D
CONVERTER ISA CARD
FEATURES
• One to Four Independent Converter
Channels
• Accepts Synchro or Resolver Inputs
• Velocity Output Signal for Each
Channel
• Low-Cost Design
• Jumper Programmable Resolution
and Bandwidth
• Jumper-Programmable Reference
Voltage Inputs
• Synthesized Ref Option Available
DESCRIPTION
The SDC-36016 is a versatile, full-size 8-bit ISA card which can be config-
ured for one to four channels of fully independent synchro-to-digital or
resolver-to-digital conversions. For each channel, the conversion process is
implemented using a DDC RDC-19222(S) 16-bit Monolithic converter.
Each converter channel can be configured for a 90V or 11.8V line-to-line dif-
ferential, synchro or resolver format, or 2V single-ended input. Each channel
can be programmed for 10-, 12-, 14-, or 16-bit resolution, and 100 Hz, 300
Hz, or a user-defined bandwidth.
Custom line-to-line voltages are also available. Consult the factory for infor-
mation regarding this feature. Each channel provides a separate reference
input signal which can be programmed to accept two voltage ranges. Also,
DDC has designed the product to operate over a frequency range of 360 Hz
to 5 kHz. Lower carrier frequency operation can be achieved with user-
defined bandwidth.
In addition to the angular position data available, each channel provides a
±4V Velocity Signal, which is accurate to 1% of the rotational rate.
Software available on request includes drivers in “C,” Pascal, LabWindows,
LabWindows/CVI, and demonstration software, which exhibits the SDC-
36016’s capabilities.
APPLICATIONS
DDC designed the SDC-36016 for modern, high-performance industrial and
military control systems. Typical applications include motor control, machine
tool control, robotics, aircraft control surface position, and process control
systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1993, 1999 Data Device Corporation
PC BUS
INTERFACE
DATA
Data Device Corporation
www.ddc-web.com
S1
BIT
STATUS
INH REGISTER
CONTROL
REGISTERS
EM, EL
ADDRESS
DECODER
S2
S3
S4
REF
SYNCHRO
OR
RESOLVER
TO
DIGITAL
CONVERTER
#1
2
ADDRESS
S1
I/O READ
I/O WRITE
I/O ENABLE
RESET
S2
S3
S4
REF
SYNCHRO
OR
RESOLVER
TO
DIGITAL
CONVERTER
#4
SDC-36016
G-11/04-0
FIGURE 1. SDC-36016 BLOCK DIAGRAM
TABLE 1. SDC-36016 SPECIFICATIONS PER CHANNEL (NOTE 1)
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; and 10% signal amplitude variation & 10% har-
monic distortion. Board has an 8 bit ISA/EISA BUS compatible output.
PARAMETER
Resolution
Accuracy
Repeatability
Differential Linearity
Reference Input
(RH,RL)
Carrier Frequency Note 4
INTRODUCTION
Each of the four converter channels are electrically identical but
can be jumper programmed independently for different options.
In addition, through software, the SDC-36016 card can be con-
figured to convert two 2-speed inputs by using one channel for
each speed input (1 coarse and 1 fine input per 2-speed input).
The software supplied with this card demonstrates this function.
The heart of each channel is DDC's RDC-19222(S) Monolithic
Resolver-to-Digital converter (ordered separately). The circuitry
external to the RDC-19222(S) provides the configuration
options. For technical information on the RDC-19222(S) consult
its data sheet.
Each channel of the SDC-36016 may be configured to accept
90 VL-L or 11.8 VL-L synchro or resolver signals, 2V single-
ended inputs, or custom line-to-line voltages. Consult the factory
regarding the custom line-to-line feature. Input levels are config-
ured by the installation of thin-film network(s) R15, R29, R43,
and R57. See FIGURE 9 and ordering information.
The synchro or resolver format for each channel is jumper pro-
grammable for the 90V and 11.8V line-to-line voltage levels. The
2V input format is resolver only (see FIGURE 8). In addition,
each channel’s resolution can be jumper programmed for 10-,
12-, 14-, or 16-bits.
Each channel also contains three jumper-programmable band-
width filtering options which consist of Low (100 Hz), High (300
Hz), and User Defined. For the User Defined option, the band-
width component values are determined by the end user,
installed onto 8-pin DIP carriers and then plugged into the appro-
priate sockets on the SDC-36016 circuit card assembly (see
FIGURES 7 and 8). A complete description of all jumper settings
is detailed in this data sheet.
The angular data for each channel can be INHIBITED (frozen) or
ENABLED (allowed to track the input angle) under computer
control. Refer to the Register section for details on the computer
programmable features. A block diagram of the SDC-36016 is
shown in FIGURE 1.
UNIT
Bits
Min
LSB
LSB
VALUE
10, 12, 14, or 16
2 to 4 ±1 LSB (Note 3)
1 max
1 max
Hz
Vrms
Ohms
Ohms
Vp
360-5000
(S)
8-30
Differential
NON(S)
2-50
100K
50K
50
100
S or NON S
40-150
500K min
250K min
200
300
transient pk
Type (Differential)
Voltage Range Note 2
Input Impedance
•Differential
•Single ended
Common-Mode Range
Signal Input
(Voltage options and mini-
mum input impedance,
balanced)
Synchro
•Zin line to line
•Zin each line to gnd
Resolver
•Zin single ended
•Zin differential
Common-Mode Range
Dynamic
Characteristics
Analog Outputs
Velocity(VEL)
Power Supply
Characteristics
Nominal Voltage
Maximum Current
Physical
Characteristics
Size
V
L-L
Ohms
Ohms
V
L-L
Ohms
Ohms
V
2
10M min
||20pF Note 5
11.8
52K
35K
11.8
70K
140K
30 max
See Table 4
See Table 5
90
195K
130K
90
260K
520K
180max
N/A
N/A
V
mA
+5
200
+12
50
-12
50
in.
(cm.)
4.2 x 13.3 x 0.77
(10.7 x 33.8 x 2.0)
SYNTHESIZED REFERENCE
The RD-19222(S) input converters contain a synthesized refer-
ence, which eliminates errors due to phase shift between the ref-
erence and the signal inputs up to 45°. Quadrature voltages in a
resolver or synchro are by definition the resulting 90° fundamen-
tal signal in the nulled out error voltage (e) in the converter. Due
to the inductive nature of resolvers and synchros, their output
signals lead the reference input signal (RH and RL). When an
uncompensated reference signal is used to demodulate the con-
trol transformer’s output, quadrature voltages are not completely
eliminated. Therefore this is the perfect solution to combat phase
shift error to 45°.
Note 1:
For complete specifications on the RDC-19222 or RDC-19222(S) con-
verters, go to the DDC Website for data sheet downloads at www.ddc-web.com.
Note 2:
S refers to RDC-19222S, NON S refers to RDC-19222.
Note 3:
Depending on converter accuracy grade and signal input configuration.
Signal input configuration using thin-film network adds 1' of error.
Note 4:
Operation with other carrier frequencies achieved with user-defined band-
width, see FIGURE 7.
Note 5:
||-in parallel with.
Data Device Corporation
www.ddc-web.com
3
SDC-36016
G-11/04-0
REGISTER ADDRESSING
The SDC-36016 is addressed in typical Base Address and Offset
fashion and uses ten contiguous bytes of memory in the I/O
address space. A Memory Map of the ten registers is listed in
TABLE 2 and the registers are described in detail in FIGURES 2
through 5.
TABLE 2. SDC-36016 MEMORY MAP
HEX OFFSET
00
01
02
03
04
05
06
07
08
09
Not Used
Channel 1 Angle LSBs
Channel 1 Angle MSBs
Channel 2 Angle LSBs
Channel 2 Angle MSBs
Channel 3 Angle LSBs
Channel 3 Angle MSBs
Channel 4 Angle LSBs
Channel 4 Angle MSBs
READ
Status Register
WRITE
Control Register
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
BASE ADDRESS SWITCH
The Base Address of the SDC-36016 is preset at the factory to
300h (HEX) as listed in TABLE 3. In this configuration the SDC-
36016 will occupy the address space of 300h to 309h (plus 310
through 31F which is not actually used by the SDC-36016 but
enables the data bus drivers). The Base Address can be
changed to any address from 000h to 3F0h in increments of 16
using TABLE 3 as a reference.
TABLE 3. SDC-36016 FACTORY SET BASE ADDRESS DIP SWITCH
SETTINGS
SWITCH
SW6
SW5
SW4
SW3
SW2
SW1
—
—
—
OFF (OPEN)
X
X
X
X
X
X
—
—
—
ON
FUNCTION
HEX 3
HEX 0
HEX 0
TABLE 4. DYNAMIC CHARACTERISTICS
LOW BANDWIDTH
PARAMETER
Reference Frequency Range
Tracking Rate (TR)
Bandwidth(Closed Loop)
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time (179° step)
UNITS
10
Hz
RPS min (typ)
Hz nom
1/sec2 nom
1/sec nom
1/sec nom
1/sec nom
1/sec nom
deg/sec2 nom
ms max
360-20K*
128 (160)
100
50K
1.22
41K
222
111
17.6K
90
HIGH BANDWIDTH
PARAMETER
Reference Frequency Range
RESOLUTION
12
360-11K*
32 (40)
100
50K
1.22
41K
222
111
4400
100
14
360-7K
8 (10)
100
50K
1.22
41K
222
111
1100
140
16
360-5K
2 (2.5)
100
50K
1.22
41K
222
111
275
320
UNITS
Hz
RPS min (typ)
Hz nom
1/sec2 nom
1/sec nom
1/sec nom
1/sec nom
1/sec nom
deg/sec2 nom
ms max
RESOLUTION
10
1.2-20K*
1152 (1440)
300
444K
1.4
323
666
333
156K
18
12
1.2-11K*
288 (360)
300
444K
1.4
323
666
333
39K
20
14
1.2-7K
72 (80)
300
444K
1.4
323
666
333
9.8K
25
16
1.2-5K
18 (20)
300
444K
1.4
323
666
333
2.4K
50
* Max carrier
for ‘S’ option is
10Khz
(RDC-19222S)
Tracking Rate (TR)
Bandwidth(Closed Loop)
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time (179° step)
Data Device Corporation
www.ddc-web.com
4
SDC-36016
G-11/04-0
TRANSFER FUNCTION
The dynamic performance of the converter can be determined
from its Transfer Function.
The open loop transfer function is as follows:
For SYNCHRO inputs the right two rows of pins in the block
below are all jumpered together. For example, pins 7-13, 8-14, 9-
15, 10-16, 11-17, and 12-18 are jumpered.
Synchro/Resolver Jumper Block Pin Configuration:
Open Loop Transfer Function =
(
S + 1
)
B
S +1
S
2
(
)
10B
A
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
where A is the gain coefficient and A
2
= A
1
A
2
and B is the frequency of lead compensation.
A
1
Error Processor, G1 Gain =
(
S + 1
)
B
S +1
S
(
)
10B
REFERENCE LEVEL JUMPER CONFIGURATION
For a 2V to 50V or 8-30V reference, jumper pins 1-4 and 3-6 are
listed in block below. For a 40V to 150V reference no jumpers are
required.
Note:
Unused jumpers can be stored at positions 1-2, 2-3, 4-5,
or 5-6. Pins 2 and 5 are unconnected.
MAX/MIN
A
VCO, G2 =
2
S
TABLE 5. VELOCITY CHARACTERISTICS
PARAMETER
Polarity
Voltage Range
Voltage Scaling
(resolution
dependent)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
±V
RPS/V
±%
PPM/°C
±%
% output
mv
µV/°C
kΩ
UNITS
TYPICAL
4.0
Typical TR (See TABLE 4)
4
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
Positive for increasing angle
Reference Level Jumper Block Configuration:
1
2
3
4
5
6
RESOLUTION JUMPER CONFIGURATION
For 10 Bits of resolution, connect jumpers 1-4 and 3-6.
For 12 Bits of resolution, connect jumper 1-4.
For 14 Bits of resolution, connect jumper 3-6.
For 16 Bits of resolution, no jumpers are installed.
Resolution Jumper Block Configuration:
JUMPER SETTINGS
Each of the four channels has an accompanying set of four
jumper blocks as listed in TABLE 6. The physical configuration of
each type of jumper block is identical for each function. The
jumper configurations are described in the following paragraphs.
TABLE 6. CHANNEL JUMPER BLOCKS
FUNCTION
SYN/RES
REF LEVEL
RESOLUTION
BANDWIDTH
CH 1
TB1
TB2
TB3
TB4
CH 2
TB5
TB6
TB7
TB8
CH 3
TB9
TB10
TB11
TB12
CH 4
TB13
TB14
TB15
TB16
WARNING!
To prevent personal injury always remove the
I/O CONNECTOR
prior to servicing the SDC-36016.
The I/O connector may contain HIGH VOLTAGES
(115V and 90V).
These voltages may be present even if the power to
the computer is turned OFF.
SYNCHRO/RESOLVER JUMPER CONFIGURATION
For RESOLVER inputs the left two rows of pins in the block
below are all jumpered together. For example, pins 1-7, 2-8, 3-9,
4-10, 5-11, and 6-12 are jumpered.
Data Device Corporation
www.ddc-web.com
5
SDC-36016
G-11/04-0
FPGA/CPLD
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