April 2004
®
AS7C331MNTD32A
AS7C331MNTD36A
3.3V 1M × 32/36 SRAM with NTD
TM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• NTD
™1
architecture for efficient bus operation
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.1/3.4/3.8 ns
• Fast OE access time: 3.1/3.4/3.8 ns
• Fully synchronous operation
• Flow-through or pipelined mode
1. NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-
marks mentioned in this document are the property of their respective owners.
• Asynchronous output enable control
• Available in 100-pin TQFP and 165-ball BGA packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Boundary scan using IEEE 1149.1 JTAG function
Logic block diagram
A[19:0]
20
D
Address
register
Burst logic
Q
20
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
FT
LBO
ZZ
32/36
D
Q
20
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
1M x 32/36
SRAM
Array
DQ[a,b,c,d]
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-200
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
4/26/04, V 1.2
-167
6
167
3.4
350
110
70
-133
7.5
133
3.8
325
100
70
Units
ns
MHz
ns
mA
mA
mA
P. 1 of 22
5
200
3.1
400
120
70
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MNTD32A
AS7C331MNTD36A
®
Pin and ball assignment
100-pin TQFP - top view
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
NC/DQPc
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
FT
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
NC/DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
92
91
90
89
88
87
86
85
84
83
82
81
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
SS
NC
V
DD
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQPa/NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration.
DQPn applies to the x36 configuration.
4/26/04, V 1.2
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Alliance Semiconductor
P. 2 of 22
AS7C331MNTD32A
AS7C331MNTD36A
®
165-ball BGA - top view for 1M X 36
1
NC
A
NC
B
DQPc
C
DQc
D
DQc
E
DQc
F
DQc
G
FT
H
DQd
J
DQd
K
DQd
L
DQd
M
DQPd
N
NC
P
LBO
R
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is
desired.
A
A
A
TMS
A0
1
TCK
A
A
A
A
NC
NC
DQd
DQd
DQd
DQd
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
NC
DQc
DQc
DQc
DQc
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
1
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
CE1
BWd
BWa
CLK
R/W
OE
A
A
NC
2
A
3
CE0
4
BWc
5
BWb
6
CE2
7
CEN
8
ADV/LD
9
A
10
A
11
NC
4/26/04, V 1.2
Alliance Semiconductor
P. 3 of 22
AS7C331MNTD32A
AS7C331MNTD36A
®
Functional description
The AS7C331MNTD32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM)
organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write
operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address
are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead'
cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random
access or read-modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD
™
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W
pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including
burst, can be stalled using the CEN=1, the clock enable input.
The AS7C331MNTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate power supply
(V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP and 165-ball BGA packages.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
4/26/04, V 1.2
Alliance Semiconductor
P. 4 of 22
AS7C331MNTD32A
AS7C331MNTD36A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
FT
TDO
TDI
TMS
TCK
ZZ
NC
I/O
I
I
I
I/O
I
I
I
I
I
I
I
O
I
I
O
I
-
Properties Description
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
SYNC
SYNC
SYNC
SYNC
ASYNC
-
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Selects Pipeline or Flow-through mode. When tied to V
DD
or left floating, enables Pipeline mode.
When driven Low, enables single register Flow-through mode.
This signal is internally pulled High.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
4/26/04, V 1.2
Alliance Semiconductor
P. 5 of 22
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