|
Preliminary Data Sheet
PT7M7443-52
µP
Supervisory Circuit
Description
The PT7M7443~7452 low-current microprocessor reset
circuits feature single or dual manual reset inputs with an
extended 6.72s setup period. Because of the extended
setup period, short switch closures (nuisance resets) are
ignored.
On all devices, the reset output asserts when any of the
monitored supply voltages drops below its specified
threshold. The reset output remains asserted for the reset
timeout period (210ms typ) after all monitored supplies
exceed their reset thresholds. The reset output is one-shot
pulse asserted for the reset timeout period (140ms min)
when selected manual reset input(s) are held low for an
extended setup timeout period of 6.72s. These devices
ignore manual reset transitions of less than 6.72s (typ).
The PT7M7443~7448 are single fixed-voltage µP
supervisors. The PT7M7443/7444 have a single extended
manual reset input. The PT7M7445/7446 have two
extended manual reset inputs. The PT7M7447/7448 have
one extended and one immediate manual reset input.
The PT7M7449~7452 have one fixed-threshold µP
supervisor and one adjustable-threshold µP supervisor.
The PT7m7449/7450 have two delayed manual reset
inputs. The PT7M7451/7452 have one delayed and one
immediate manual reset input.
The PT7M7443~7452 have an active-low /RESET with
push-pull or open-drain output logic options. These
devices, offered in small SOT package, are fully
guaranteed over the extended temperature range (-40℃
to +85℃).
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Features
•
•
•
•
•
•
•
•
•
•
•
Single- or Dual-Supply Voltage Monitors
Precision Factory-Set Reset Thresholds from 1.6V to
4.6V
Adjustable Threshold to Monitor Voltages Down to
0.63V (PT7M7449~7452)
Single or Dual Manual Reset Inputs with Extended
6.72s Setup Period
Optional Short Setup Time Manual Reset Input
(PT7M7447/7448/7451/7452)
Immune to Short Voltage Transients
Low 3uA Supply Current
Guaranteed Valid Reset Down to VDD=1.0V
Active-Low
Outputs
/RESET(Push-Pull
or
Open-Drain)
140ms(min) Reset Timeout Period
Small 5 and 6-Pin SOT23 Packages
Ordering Information
Part Number
PT7M7443xTAE
PT7M7444xTAE
PT7M7445xTAE
PT7M7446xTAE
PT7M7447xTAE
PT7M7448xTAE
PT7M7449xTAE
PT7M7450xTAE
PT7M7451xTAE
PT7M7452xTAE
Package
lead-free SOT23-5
lead-free SOT23-5
lead-free SOT23-5
lead-free SOT23-5
lead-free SOT23-5
lead-free SOT23-5
lead-free SOT23-6
Lead-free SOT23-6
lead-free SOT23-6
lead-free SOT23-6
Note:
suffix “x” represents 9 kinds of factory trimmed reset
threshold voltage. Please see below table.
Applications
•
Monitoring lithiumion (Li
+
) cells or multicell
alkaline/ NiCd/ NiMH power supplies.
Table 1
Suffix “x” definition of PT7M7443~7452
Suffix x
L
M
T
Reset threshold (V)
4.63
4.38
3.08
S
2.93
R
2.63
Z
2.32
Y
2.19
W
1.67
V
1.58
PT0289(07/07)
1
Ver: 0
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Preliminary Data Sheet
PT7M7443-52
µP
Supervisory Circuit
Table 2
Function comparison of PT7M7443~7452
Push-Pull
Open-Drain
PART
Active-Low
Active-Low
Output
Output
PT7M7443
√
-
PT7M7444
-
√
PT7M7445
√
-
PT7M7446
-
√
PT7M7447
√
-
PT7M7448
-
√
PT7M7449
√
-
PT7M7450
-
√
PT7M7451
√
-
PT7M7452
-
√
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
/MR1
Setup
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
/MR2
Setup
-
-
6.72s
6.72s
-
-
6.72s
6.72s
-
-
MR2
(No
Setup)
-
-
-
-
√
√
-
-
√
√
RSTIN
-
-
-
-
-
-
√
√
√
√
Package
SOT23-5
SOT23-6
Block Diagram
PT0289(07/07)
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Ver: 0
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Preliminary Data Sheet
PT7M7443-52
µP
Supervisory Circuit
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Pin Configuration
Pin Description
7443/44
1
7445/46
2
Pin
7447/48
2
7449/50
2
7451/52
2
Name
GND
Function
Ground
Active-Low Push-Pull or Open-Drain Output.
/RESET changes from high to low when V
DD
or RSTIN
drops below its selected reset threshold and remains low
for the 210ms reset timeout period after all monitored
power-supply inputs exceed their selected reset
thresholds. /RESET is one-shot pulsed low for the reset
timeout period (140ms min) after selected manual reset
inputs are asserted longer than the specified setup period.
For the open-drain output, use a minimum 20kΩ pull-up
resistor to V
DD
.
Manual Reset Input, Active Low.
Internal 50kΩ pull-
up to VDD. Pull /MR1 low for the typical input pulse
width (6.72s) to one-shot pulse /RESET for the reset
timeout period.
Manual Reset Input, Active Low.
Pull both /MR1 and
/MR2 low for the typical input pulse width (6.72s) to
one-shot pulse /RESET for the reset timeout period.
V
DD
Voltage Input.
Power supply and input for the
primary microprocessor voltage reset monitor.
Manual Reset Input, Active Low.
Internal 50kΩ pull-
up to V
DD
. Pull both /MR1 and /MR2 low for the typical
input pulse width (6.72s) to one-shot pulse /RESET for
the reset timeout period.
Manual Reset Input.
Pull theMR2 high to immediately
one-shot pulse /RESET for the reset timeout peiod.
Reset Input.
High-impedance input to the adjustable
reset comparator. Connect RSTIN to the center point of
an external resistor-divider to set the threshold of the
externally monitored voltage.
Not Connected.
Ver: 0
3
3
1
1
1
1
/RESET
4
--
3
--
3
/MR1
--
5
--
--
--
2
PT0289(07/07)
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4
5
--
--
--
--
4
--
5
--
--
3
4
6
--
5
--
--
4
--
6
5
--
VDD
/MR2
MR2
RSTIN
NC
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Preliminary Data Sheet
PT7M7443-52
µP
Supervisory Circuit
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Function Description
•
Reset Output
The reset output is typically connected to the reset input
of a microprocessor (µP). A µP’s reset input starts or
restarts the µP in a known state. The PT7M7443~7452
µP supervisory circuits provide the reset logic to prevent
code-execution errors during power-up, power-down and
brownout conditions (see Figure 8 Typical Operating
Circuit).
/RESET changes from high to low whenever the
monitored voltages (RSTIN or V
DD
) drop below the reset
threshold voltages. Once V
RSTIN
and V
DD
exceed their
respective reset threshold voltages, /RESET remains low
for the reset timeout period and than goes high. /RESET
is one-shot pulsed whenever selected manual reset inputs
are asserted. /RESET stays asserted for the normal reset
timeout period (140ms).
/RESET is guaranteed to be in the proper output logic
state for V
DD
inputs
≥
1V.
Figure 1 Typical Operating Circuit
•
Manual Reset Input Options
Unlike typical manual reset functions associated with
supervisors, each device in the PT7M7443~ 7452 family
includes at lease one manual reset input, which must be
held logic-low for an extended setup period (6.72 typ)
before the /RESET output asserts. When valid manual reset
input conditions/setup periods are met, the /RESET output
is one-shot pulse asserted low for a fixed reset timeout
period (140ms min). Existing front-panel pushbutton
switches (i.e., power on/off, channel up/down, or mode
select) can be used to drive the manual reset inputs. The
extended manual reset setup period prevents nuisance
system resets during normal front-panel usage or resulting
from inadvertent short-term pushbutton closure.
PT7M7443/7444, PT7M7447/7448, and PT7M7451/7452
include a single manual reset input with extended setup
period (/MR1). The PT7M7445/7446 and PT7M7449/7450
include two manual reset inputs (/MR1 and /MR2) with
extended setup periods. For dual /MR1, /MR2 devices, both
inputs must be held low simultaneously for the extended
setup period (6.72s typ) before the reset output is pulse
asserted. The dual extended setup provides greater protection
from nuisance resets. (For example, the user or service
technician is informed to simultaneously push both the on/off
button and the channel-select button for 6.72s to reset the
system.)
Figure 2 PT7M7443/7444 Manual Reset Timing
210ms
MR1
6.72s
MR2
RESET
Figure 3 PT7M7445/7446/7449/7450 Manual Reset
Timing Diagram
PT0289(07/07)
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Ver: 0
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Preliminary Data Sheet
PT7M7443-52
µP
Supervisory Circuit
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The PT7M7443~7452 /RESET output is pulse asserted
once for the reset timeout period after each valid manual
reset input condition. At least one manual reset input must
be released (go high) and then be driven low for the
extended setup period before /RESET asserts again.
Internal timing circuitry debounces low-to-high manual
reset logic transitions, so no external circuitry is required.
Figure 9 illustrates the single manual reset function of the
PT7M443/7444 single-voltage monitors, and Figure 10
represents the dual manual reset function of the
PT7M7445/7446 and PT7M7449/7450.
The PT7M7447/7448 and PT7M7451/7452 include both
an extended setup period and immediate setup period
manual reset inputs. A low-to-high MR2 rising edge
transition immediately pulse asserts the /RESET output for
the reset timeout period (140ms min). If the
PT7M7447/7448 and PT7M7451/7452 MR2 input senses
another rising edge before the end of the 140ms timeout
period (Figure 11), the internal timer clears and begins
counting again. If no rising edges are detected within the
210ms timeout period, /RESET deasserts. The high-to-low
transition on MR2 input is internally debounced for 210ms
to ensure that there are no false /RESET assertions when
MR2 is driven from high to low (Figure 12). The MR2
input can be used for system test purposes or smart-card-
detect applications (see
Applications Information
section).
Figure 4 PT7M7447/7448/7451/7452 MR2 Assertion
Debouncing Timing Diagram
Figure 5 PT7M7447/7448/7451/7452 MR2 Deassertion
Debouncing Timing Diagram
Application Information
•
Adjustable Input Voltage (RSTIN)
The PT7M7449~7452 monitor the voltage on RSTIN using an
adjustable reset threshold set with an external resistor voltage-divider
(see Figure 14). Use the following formula to calculate the externally
monitored voltage (V
MON-TH
):
V
MON
−
TH
=
V
TH
−
RSTIN
×
(
R
1
+
R
2
)
R
2
Where V
MON-TH
is the desired reset threshold voltage and V
TH-RSTIN
is
the reset input threshold (0.63V). Resistors R1 and R2 can have very
high values to minimize current consumption because of low leakage
currents. Set R2 to some conveniently high value (250kΩ, for
example), and calculate R1 based on the desired reset threshold
voltage, using the following formula:
R
1
=
R
2
×
(
V
MON
−
TH
V
TH
−
RSTIN
−
1
)
Ω
Figure 6 PT7M7449~7452 Calculating the
Monitored Threshold Voltages
PT0289(07/07)
5
Ver: 0
FPGA/CPLD
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