Philips Semiconductors
Product specification
Triple high-speed Analog-to-Digital
Converter (ADC)
FEATURES
•
Triple 8-bit ADC
•
Sampling rate up to 100 MHz
•
IC controllable via a serial interface, which can be either
I
2
C-bus or 3-wire, selected via a TTL input pin
•
IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)
•
3 clamps for programming a clamping code between
−63.5
and +64 in steps of
1
⁄
2
LSB
•
3 controllable amplifiers: gain controlled via the serial
interface to produce a full scale resolution of
1
⁄
2
LSB
peak-to-peak
•
Amplifier bandwidth of 250 MHz
•
Low gain variation with temperature
•
PLL, controllable via the serial interface to generate the
ADC clock, which can be locked to a line frequency from
15 to 280 kHz
•
Integrated PLL divider
•
Programmable phase clock adjustment cells
•
Internal voltage regulators
•
TTL compatible digital inputs and outputs
•
Chip enable high-impedance ADC output
•
Power-down mode
•
Possibility to use up to four ICs in the same system,
using the I
2
C-bus interface, or more, using the 3-wire
serial interface
•
1 W power dissipation.
APPLICATIONS
•
R, G and B high-speed digitizing
•
LCD panels drive
•
LCD projection systems
•
VGA and higher resolutions
•
Using two ICs in parallel, higher display resolution can
be obtained; 200 MHz pixel frequency.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA8752AH/6
TDA8752AH/8
DESCRIPTION
GENERAL DESCRIPTION
TDA8752A
The TDA8752A is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.
The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I
2
C-bus or 3-wire
serial bus, selected via a logic input).
The IC also includes a PLL that can be locked on the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.
It is possible to set the TDA8752A serial bus address
between four fixed values, in the event that several
TDA8752A ICs are used in a system, using the I
2
C-bus
interface (for example, two ICs used in an odd/even
configuration).
VERSION
SOT317-2
SAMPLING
FREQUENCY
(MHz)
60
100
QFP100 plastic quad flat package; 100 leads (lead length
1.95 mm); body 14
×
20
×
2.8 mm
1999 Feb 24
2
Philips Semiconductors
Product specification
Triple high-speed Analog-to-Digital
Converter (ADC)
QUICK REFERENCE DATA
SYMBOL
V
CCA
V
DDD
V
CCD
V
CCO
V
CCA(PLL)
V
CCO(PLL)
I
CCA
I
DDD
I
CCD
I
CCO
I
CCA(PLL)
I
CCO(PLL)
f
CLK
f
ref(PLL)
f
VCO
INL
PARAMETER
analog supply voltage
logic supply voltage
digital supply voltage
output stages supply voltage
analog PLL supply voltage
output PLL supply voltage
analog supply current
logic supply current
digital supply current
output stages supply current
analog PLL supply current
output PLL supply current
maximum clock frequency
PLL reference clock frequency
VCO output clock frequency
DC integral non linearity
from analog input to
digital output; full-scale;
ramp input;
f
CLK
= 100 MHz
from analog input to
digital output; full-scale;
ramp input;
f
CLK
= 100 MHz
V
ref
= 2.5 V with
100 ppm/°C maximum
−3
dB; T
amb
= 25
°C
TDA8752A/6
TDA8752A/8
f
CLK
= 100 MHz;
ramp input
for I
2
C-bus and 3-wire
for R, G and B channels
CONDITIONS
for R, G and B channels
for I
2
C-bus and 3-wire
MIN.
4.75
4.75
4.75
4.75
4.75
4.75
−
−
−
−
−
−
60
100
15
12
−
TYP.
5.0
5.0
5.0
5.0
5.0
5.0
120
1.0
40
6
28
5
−
−
−
−
±0.5
TDA8752A
MAX.
5.25
5.25
5.25
5.25
5.25
5.25
−
−
−
−
−
−
−
−
280
100
±1.5
UNIT
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
MHz
MHz
kHz
MHz
LSB
DNL
DC differential non linearity
−
±0.5
±1.0
LSB
∆G
amp
/T
B
t
set
DR
PLL
P
tot
j
PLL(rms)
amplifier gain stability as a function of
temperature
amplifier bandwidth
settling time of the ADC block plus AGC
PLL divider ratio
total power consumption
maximum PLL phase jitter (RMS value)
−
250
−
−
−
−
1.0
0.3
200
−
6
4095
−
−
ppm/°C
MHz
ns
input signal settling
−
time < 1 ns; T
amb
= 25
°C
100
f
CLK
= 100 MHz;
ramp input
f
ref
= 66.67 kHz;
f
CLK
= 100 MHz
−
−
W
ns
1999 Feb 24
3
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