8M
×
72-Bit EDO- DRAM Module
(ECC - Module)
168 pin buffered DIMM Module
HYM 72V8025GS-50/-60
HYM 72V8035GS-50/-60
•
168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module
for PC main memory applications
1 bank 8 M x 72 organisation
Optimized for ECC applications
Hyper Page Mode - EDO Operation
Performance:
-50
tRAC
tCAC
tAA
tRC
tHPC
RAS Access Time
CAS Access Time
Access Time from Address
Cycle Time
EDO Mode Cycle Time
50 ns
18 ns
30 ns
84 ns
20 ns
-60
60 ns
20 ns
35 ns
104 ns
25 ns
•
•
•
•
•
•
•
•
•
•
•
•
•
Single + 3.3V
±
0.3 V supply
CAS-before-RAS refresh, RAS-only refresh
Decoupling capacitors mounted on substrate
All inputs, outputs and clock fully LVTTL & LVCMOS compatible
4 Byte interleave enabled, Dual Address inputs (A0/B0)
Buffered inputs excepts RAS and DQ
Parallel Presence Detects
Utilizes nine 8M
×
8 -DRAMs and BiCMOS buffers/line drivers VT244A
Two versions: HYM 72V8035GS with SOJ-components ( 9 mm module thickness)
HYM 72V8025GS with TSOPII-components ( 4 mm module thickness)
4048 refresh cycles / 64 ms with 12 / 11 addressing
Gold contact pad
Double sided module with 25.35 mm (1000 mil) height
•
•
•
Semiconductor Group
1
3.97
HYM72V8025/35GS-50/-60
8M x 72-ECC EDO-Module
The HYM 72V8025/35GS-50/-60 is a 64 MByte DRAM module organized as 8 388 608 words by 72-
bit in a 168-pin, dual read-out, single-in-line package comprising nine HYB3165805AJ/AT 8M
×
8
DRAMs in 400 mil wide SOJ or TSOPII - packages mounted together with ceramic decoupling
capacitors on a PC board. All inputs except RAS and DQ are buffered by using BiCMOS buffers/
line drivers.
Each HYB3165805AJ/AT is described in the data sheet and is fully electrically tested and
processed according to Siemens standard quality procedure prior to module assembly. After
assembly onto the board, a further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
Ordering Information
Type
HYM 72V8025GS-50
HYM 72V8025GS-60
HYM 72V8035GS-50
HYM 72V8035GS-60
Ordering Code
Package
L-DIM-168-3
L-DIM-168-3
L-DIM-168-3
L-DIM-168-3
Descriptions
EDO-DRAM module (access time 50 ns)
EDO-DRAM module (access time 60 ns)
EDO-DRAM module (access time 50 ns)
EDO-DRAM module (access time 60 ns)
Pin Names
A0-A12,B0
A0-A11,B0
DQ0 - DQ71
RAS0, RAS2
CAS0 , CAS2
WE0, WE2
OE0, OE2
Vcc
Vss
PD1 - PD8
PDE
ID0 , ID1
N.C.
Presence-Detect and ID-pin Truth Table:
Module
HYM 728025/35GS-50
HYM 728025/35GS-60
ID0
Vss
Vss
ID1
Vss
Vss
PD1
1
1
PD2
0
0
PD3
1
1
PD4
1
1
PD5
1
1
PD6
0
1
PD7
0
1
PD8
0
0
Row Address Inputs
Column Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Output Enable
Power (+3.3 Volt)
Ground
Presence Detect Pins
Presence Detect Enable
ID indentification bit
No Connection
Note:
1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high
level all PD terminal are in tri-state.
Semiconductor Group
2
HYM72V8025/35GS-50/-60
8M x 72-ECC EDO-Module
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
DQ16
DQ17
VSS
NC
NC
VCC
WE0
CAS0
NC
RAS0
OE0
VSS
A0
A2
A4
A6
A8
A10
NC
VCC
NC
NC
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
VSS
OE2
RAS2
CAS4
NC
WE2
VCC
NC
NC
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
NC
NC
NC
NC
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
VSS
PD1
PD3
PD5
PD7
ID0 (VSS)
VCC
PIN #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
VSS
DQ36
DQ37
DQ38
DQ39
VCC
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ50
DQ51
DQ52
DQ53
VSS
NC
NC
VCC
NC
NC
NC
NC
NC
VSS
A1
A3
A5
A7
A9
A11
NC
VCC
NC
B0
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
VSS
NC
NC
NC
NC
PDE
VCC
NC
NC
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
NC
NC
NC
NC
DQ61
DQ62
DQ63
VSS
DQ64
DQ65
DQ66
DQ67
VCC
DQ68
DQ69
DQ70
DQ71
VSS
PD2
PD4
PD6
PD8
ID1 (VSS)
VCC
Semiconductor Group
3
HYM72V8025/35GS-50/-60
8M x 72-ECC EDO-Module
RAS0
CAS0
WE0
OE0
RAS2
CAS4
WE2
OE2
DQ0-DQ7
I/O1-I/O8
D0
DQ40-DQ47
I/O1-I/O8
D5
DQ8-DQ15
I/O1-I/O8
D1
DQ48-DQ55
I/O1-I/O8
D6
DQ16-DQ23
I/O1-I/O8
D2
DQ56-DQ63
I/O1-I/O8
D7
DQ24-DQ31
I/O1-I/O8
D3
DQ64-DQ71
I/O1-I/O8
D8
DQ32-DQ39
I/O1-I/O8
D4
A0
B0
A1-A11
D0 - D4
D5 - D8
D0 - D8
Vcc
Vss
D0-D8, buffers
PDE
Vcc or Vss
PD1-PD8
Block Diagram
Semiconductor Group
4
HYM72V8025/35GS-50/-60
8M x 72-ECC EDO-Module
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range...................................................................................... – 55 to + 125 °C
Input/output voltage ............................................................................... -0.5 to min (Vcc+0.5, 4.6) V
Power supply voltage................................................................................................. – 0.5V to 4.6 V
Power dissipation.................................................................................................................... 5,8 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C;
V
CC
= 3.3 V
±
0.3 V
Parameter
Input high voltage
Input low voltage
Output high voltage (LVTTL)
Output „ “level voltage (
I
OUT
= – 2 mA)
H
Output low voltage (LVTTL)
Output „ “ level voltage (
I
OUT
= + 2 mA)
L
Output high voltage (LVCMOS)
Output „ “level voltage (
I
OUT
= – 100
µA)
H
Output low voltage (LVCMOS)
Output „ “ level voltage (
I
OUT
= + 100
µA)
L
Input leakage current
(0 V <
V
IN
< Vcc, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< Vcc)
Average
V
CC
supply current:
-50 version
-60 version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
Standby
V
CC
supply current
(RAS = CAS =2.4V, one address change
within 15,6
µs
trc)
Symbol
Limit Values
min.
max.
Vcc + 0.3 V
0.8
–
0.4
–
0.2
20
20
V
V
V
V
V
µA
µA
2.0
– 0.3
2.4
–
Vcc-0.2
–
– 20
– 20
Unit
Test
Condition
1)
1)
1)
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
–
–
1260
1080
mA
mA
2) 3) 4)
I
CC2
–
50
mA
–
Semiconductor Group
5
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