HY5DU1291622
4 Banks x 2M x 16Bit DOUBLE DATA RATE SDRAM
PRELIMINARY
DESCRIPTION
The Hyundai HY5DU1291622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited
for the main memory applications which require large memory density and high bandwidth. HY5DU1291622 is orga-
nized as 4 banks of 2,097,152x16.
HY5DU1291622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data
strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The
data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage
levels are compatible with SSTL_2.
Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 / 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or
interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved
than that of traditional (single data rate) Synchronous DRAM.
FEATURES
•
•
2.5V for V
DD
and 2.5V for V
DDQ
power supplies
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
/QFC & Half Strength Driver optioned by EMRS
•
•
Fully differential clock operations(CLK & CLK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes(LDQS/UDQS) and Write
masks(LDM/UDM) latched on both rising and falling
edges of the clock
Data outputs on LDQS/UDQS edges when read
(edged DQ)
•
•
•
•
Write mask byte controls by LDM and UDM
Bytewide data strobes by LDQS and UDQS
Programmable CAS Latency 2 / 2.5 / 3 supported
Write Operations with 1 Clock Write Latency
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
•
Data inputs on LDQS/UDQS centers when write
(centered DQ)
Data strobes synchronized with output data for read
and input data for write
Delay Locked Loop(DLL) installed with DLL reset
mode
•
•
•
•
•
•
•
•
•
•
ORDERING INFORMATION
Part No.
HY5DU1291622TC-75
HY5DU1291622TC-8
HY5DU1291622TC-10
V
DD
=2.5V
V
DDQ
=2.5V
Power Suppy
Clock Frequency
133MHz
125MHz
100MHz
Organization
Interface
Package
400mil 66pin
TSOP II
4Banks x 2Mbit x16
SSTL_2
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Dec.98
HY5DU1291622
PIN CONFIGURATION
V
DD
DQ0
VDDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DDQ
LDQS
NC
V
DD
/QFC, NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
TOP VIEW
2
3
4
5
6
7
8
9
10
11
12
13
14
15 400mil X 875mil
16 66 Pin TSOP-II
17 0.65mm Pin Pitch
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTION
PIN
CLK, CLK
CKE
CS
BA0, BA1
A0 ~ A11
PIN NAME
Differential Clock Input
Clock Enable
Chip Select
Bank Select Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Write Mask
Data Input/Output Strobe
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
Reference Voltage
DQ FET Switch Control
(optional)
No Connection
DESCRIPTION
The system clock input. All of the inputs are letched on the rising edges of the
clock except DQi, LDQS/UDQS and LDM/UDM that are sampled on the both.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
Enables or disables all inputs except CLK/CLK, CKE, LDQS/UDQS and
LDM/UDM.
Selects bank to be activated during either RAS or CAS activity.
Selects bank to be read/written during either RAS or CAS activity.
Row Address : A0 ~ A11, Column Address : A0 ~ A8
Auto-precharge flag : A10
RAS, CAS and WE define the operations.
Refer function truth table for details.
Masks input data in write mode.
Active on the both edges for Data Input and Output.
Multiplexed data input / output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers for Noise immunity.
Reference voltage for inputs for SSTL interface.
Controls FET Switches on DQs used for reduction of Impedance.
No connection.
2
RAS, CAS, WE
LDM, UDM
LDQS, UDQS
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
/QFC
NC
Rev. 0.1/Dec.98
HY5DU1291622
FUNCTIONAL BLOCK DIAGRAM
4banks x 2Mbit x 16 I/O Double data rate Synchronous DRAM
16
DS
Input Buffer
Write Data Register
2-bit Prefetch Unit
32
Bank
Control
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM
Mode
Register
Command
Decoder
1Mx16/Bank0
2-bit Prefetch Unit
Sense AMP
Output Buffer
1Mx16/Bank1
1Mx16/Bank2
1Mx16/Bank3
Row
Decoder
32
16
DQ[0:15]
Column Decoder
DQS
ADD
Address
Buffer
Column Address
Counter
CLK_DLL
Data Strobe
Transmitter
Data Strobe
Receiver
DS
CLK
DLL
Block
Mode
Register
Rev. 0.1/Dec.98
3
HY5DU1291622
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1
260
⋅
10
Rating
°C
°C
V
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITIONS
(TA=0 to 70°C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Symbol
Min
2.3
2.3
V
REF
+ 0.18
-0.3
V
REF
- 0.04
1.15
Typ.
2.5
2.5
-
-
V
REF
1.25
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.18
V
REF
+ 0.04
1.35
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with
≤5ns
of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING TEST CONDITIONS
(TA=0 to 70°C, Voltage referenced to V
SS
= 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (V
IH
, min)
AC Input Low Level Voltage (V
IL
, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Value
V
DDQ
x 0.5
V
DDQ
x 0.5
V
REF
+ 0.35
V
REF
- 0.35
V
REF
V
TT
Unit
V
V
V
V
V
V
Rev. 0.1/Dec.98
4
HY5DU1291622
AC OPERATING TEST CONDITIONS
(TA=0 to 70°C, Voltage referenced to V
SS
= 0V)
Parameter
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (R
T
)
Series Resistor (R
S
)
Output Load Capacitance for Access Time Measurement (C
L
)
Value
1.5
1
50
25
30
- continued -
Unit
V
V/ns
Ω
Ω
pF
CAPACITANCE
(T
A
=25°C, f=1MHz)
Parameter
Input Capacitance
Clock Capacitance
Data Input / Output Capacitance
Pin
A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE
CLK, CLK
DQ0 ~ DQ15, LDQS, UDQS, LDM, UDM
Symbol
C
IN
C
CLK
C
IO
Min
2.5
2.5
4.0
Max
3.5
3.5
5.5
Unit
pF
pF
pF
OUTPUT LOAD CIRCUIT
V
TT
V
TT
R
T
=50Ω
R
T
=50Ω
Output
R
S
=25Ω
Zo=50Ω
V
REF
C
L
=30pF
Rev. 0.1/Dec.98
5
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