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HCS109K/SAMPLE

产品描述HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, METAL SEALED, CERAMIC, DFP-16
产品类别逻辑    逻辑   
文件大小173KB，共9页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

HCS109K/SAMPLE概述

HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, METAL SEALED, CERAMIC, DFP-16

HCS109K/SAMPLE规格参数

参数名称属性值
厂商名称Renesas(瑞萨电子)
零件包装代码DFP
包装说明DFP,
针数16
Reach Compliance Codeunknown
系列HC/UH
JESD-30 代码R-CDFP-F16
逻辑集成电路类型J-KBAR FLIP-FLOP
位数2
功能数量2
端子数量16
输出极性COMPLEMENTARY
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DFP
封装形状RECTANGULAR
封装形式FLATPACK
传播延迟（tpd）30 ns
认证状态Not Qualified
座面最大高度2.92 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
触发器类型POSITIVE EDGE
宽度6.73 mm

HCS109K/SAMPLE文档预览

HCS109MS
September 1995
Radiation Hardened
Dual JK Flip Flop
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
R1
J1
K1
CP1
S1
Q1
Q1
GND
1
2
3
4
5
6
7
8
16 VCC
15 R2
14 J2
13 K2
12 CP2
11 S2
10 Q2
9 Q2
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii
≤
5µA at VOL, VOH
-9
Errors/Bit-Day
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
R1
J1
K1
CP1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
R2
J2
K2
CP2
S2
Q2
Q2
Description
The Intersil HCS109MS is a Radiation Hardened Dual JK
Flip Flop with set and reset. The flip flop changes state with
the positive transition of the clock (CP1 or CP2).
The HCS109MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS109MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
S1
Q1
Q1
GND
Ordering Information
PART NUMBER
HCS109DMSR
HCS109KMSR
HCS109D/Sample
HCS109K/Sample
HCS109HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
File Number
103
518748
2466.2
HCS109MS
Functional Diagram
5 (11)
S
2 (14)
J
3 (13)
K
4 (12)
CP
1 (15)
R
VCC
GND
16
8
6 (10)
Q
7 (9)
Q
J
S
F/F
Q
K
CL CL R Q
TRUTH TABLE
INPUTS
S
L
H
L
H
H
H
H
H
R
H
L
L
H
H
H
H
H
L
CP
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
H
No Change
Q
H
L
H*
L
Toggle
No Change
L
OUTPUTS
Q
L
H
H*
H
*Unpredictable and unstable condition if both S and R go high simultaneously
L = Logic Level Low
H = Logic Level High
= Transition from Low to High Level
Spec Number
104
518748
Specifications HCS109MS
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output.
. . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73
24
o
C/W
Ceramic Flatpack Package . . . . . . . . . . . 114
o
C/W
29
o
C/W
o
C Ambient
Maximum Package Power Dissipation at +125
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/
o
C
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .500ns Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
1
2, 3
Output Current
(Sink)
IOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
1
2, 3
Output Current
(Source)
IOH
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or
GND
1
2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
4.8
4.0
-4.8
-4.0
-
MAX
20
400
-
-
-
-
0.1
UNITS
µA
µA
mA
mA
mA
mA
V
PARAMETER
Quiescent Current
SYMBOL
ICC
(NOTE 1)
CONDITIONS
VCC = 5.5V,
VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC
-0.1
VCC
-0.1
-
-
-
-
V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
V
1
2, 3
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
±0.5
±5.0
-
µA
µA
-
Noise Immunity
Functional Test
FN
VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
7, 8A, 8B
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
Spec Number
105
518748
Specifications HCS109MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V
VCC = 4.5V
TPHL
VCC = 4.5V
VCC = 4.5V
S to Q
TPLH
VCC = 4.5V
VCC = 4.5V
S to Q
TPHL
VCC = 4.5V
VCC = 4.5V
R to Q
TPHL
VCC = 4.5V
VCC = 4.5V
R to Q
TPLH
VCC = 4.5V
VCC = 4.5V
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
GROUP A
SUBGROUPS
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
2
2
2
2
2
2
2
2
2
2
2
2
MAX
26
30
30
35
19
23
31
33
31
33
31
33
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
CP to Q, Q
SYMBOL
TPLH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
Input Capacitance
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
NOTES
1
1
CIN
VCC = 5.0V, f = 1MHz
1
1
Output Transition
Time
Max Operating
Frequency
Setup Time JK to
CP
Hold Time JK to CP
TTHL
TTLH
FMAX
VCC = 4.5V
1
1
VCC = 4.5V
1
1
TSU
VCC = 4.5V
1
1
TH
VCC = 4.5V
1
1
Removal Time R,
S to CP
Pulse Width CP
TREM
VCC = 4.5V
1
1
TW
VCC = 4.5V
1
1
Pulse Width R, S
TW
VCC = 4.5V
1
1
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
-
-
-
-
-
-
-
-
18
27
3
3
18
27
18
27
18
27
MAX
41
56
10
10
15
22
30
20
-
-
-
-
-
-
-
-
-
-
UNITS
pF
pF
pF
pF
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Spec Number
106
518748
Specifications HCS109MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
IOL
(NOTES 1, 2)
CONDITIONS
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
TEMPERATURE
+25
o
C
+25
o
C
MIN
-
4.0
MAX
0.4
-
UNITS
mA
mA
Output Current
(Source)
Output Voltage Low
IOH
+25
o
C
-4.0
-
mA
VOL
+25
o
C
-
0.1
V
Output Voltage High
VOH
+25
o
C
VCC
-0.1
-
-
-
V
Input Leakage Current
Noise Immunity
Functional Test
CP to Q, Q
IIN
FN
+25
o
C
+25
o
C
±5
-
µA
-
TPLH
TPHL
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
2
2
2
2
2
2
30
35
23
33
33
33
ns
ns
ns
ns
ns
ns
S to Q
S to Q
R to Q
R to Q
NOTES:
TPLH
TPHL
TPHL
TPLH
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25
o
C)
GROUP B
SUBGROUP
5
5
PARAMETER
ICC
IOL/IOH
DELTA LIMIT
6µA
-15% of 0 Hour
Spec Number
107
518748
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HCS109K/SAMPLE相似产品对比

HCS109K/SAMPLE HCS109D/SAMPLE
描述 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, METAL SEALED, CERAMIC, DFP-16 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, METAL SEALED, SIDE BRAZED, CERAMIC, DIP-16
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子)
零件包装代码 DFP DIP
包装说明 DFP, DIP,
针数 16 16
Reach Compliance Code unknown unknown
系列 HC/UH HC/UH
JESD-30 代码 R-CDFP-F16 R-CDIP-T16
逻辑集成电路类型 J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP
位数 2 2
功能数量 2 2
端子数量 16 16
输出极性 COMPLEMENTARY COMPLEMENTARY
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DFP DIP
封装形状 RECTANGULAR RECTANGULAR
封装形式 FLATPACK IN-LINE
传播延迟（tpd） 30 ns 30 ns
认证状态 Not Qualified Not Qualified
座面最大高度 2.92 mm 5.08 mm
最大供电电压 (Vsup) 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V
表面贴装 YES NO
技术 CMOS CMOS
端子形式 FLAT THROUGH-HOLE
端子节距 1.27 mm 2.54 mm
端子位置 DUAL DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE
宽度 6.73 mm 7.62 mm

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