AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM MCP
25mm x 32mm, 219 PBGA
1.27mm Pitch
Revision 0.3
(May 31,06) -for new lower ICC limits
Development
/ ADVANCE Information
Product
Information is subject to change or be canceled without notice!
Austin Semiconductor, Inc.
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AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
Features
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Performance: 100MHz, 125MHz and 133MHz
Core Supply Voltage = 3.3v +/- 0.3v
IO Supply Voltage = 3.3v +/- 0.3v
Internal, pipeline, architecture
Single Clock Input
Positive edge; Command execution
DLL for alignment of DQ and DQS transitions
Four internal banks for concurrent operation
Data Mask (DM) for masking write data
Programmable IOL/IOH
Programmable Burst length: 1,2,4,8 or full page
Auto Precharge
Self Refresh Mode on /IT and /ET devices
This architecture is compatible with the 2n rule of
PREFETCH architectures, but it also allows the column
address to be changed on every clock cycle to achieve a
high-speed, fully random access. PRECHARGING one
bank while accessing one of the other three banks will
hide the precharge cycles and provide seamless array
access at rated speed.
Initialization
Austin Semiconductor’s AS4SD16M72PBG is like all
other SDRAM devices and for correct functional
operation must be properly initialized in a predefined
manor, following the allowable functional modes.
Operation of the device outside of the prescribed modes
may result in undefined device operation. Once power is
applied to VDD and VDDQ and the clock is stable, the
device requires a 100us delay prior to issuing a command
other than a COMMAND INHIBIT or NOP. Starting at
some point during this 100us period and continuing at
least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100us delay has been satisfied with at least one
COMMAND INHIBIT or NOP, a PRECHARGE
command should be applied. All banks must then be
PRECHARGED, thereby placing the device in the all
banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register
programming. Because the mode register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
Silicon Base:
•Micron: Die equivalency to MT48LC16M16A2
General Description
Austin Semiconductor’s 1.2Gb, Synchronous DRAM is a high
speed CMOS MCP and is packaged in a 25mm x 32mm, 219
PBGA with a ball pitch of 1.27mm. This device contains (5)
x16 synchronous dynamic random access die, each containing
a total density of 268,435,456 bits. The end organization of
the MCP is 16M x 80.
Read and Write accesses to the array are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations, as prescribed by the
programmed sequence. Accesses begin with the registration
of an ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank; A0-A12 select
the row). The address bits registered at the initiation of
READ or WRITE are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, 8 or full page, with a burst terminate
option. An AUTO PRECHARGE function may be enabled to
provide a self-timed row precharge that is initiated at the end
of the burst sequence.
Austin Semiconductor’s AS4SD16M72PBG device uses an
internal pipeline architecture to achieve high speed operation.
Austin Semiconductor, Inc.
Register Definition [MODE REGISTER]
The mode register is used to define the specific mode of
operation of the SDRAM MCP. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a WRITE burst mode.
The MODE REGISTER is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
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Specifies the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE BURST mode and M10,
M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the
MODE REGISTER.
The MODE REGISTER must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
N + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met, If
a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will be valid by T2.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Operating Mode
Burst Length
READ and WRITE accesses to the SDRAM are burst
oriented, with the burst length being programmable. The
burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1,2,4 and 8 locations are available
for both the sequential and the interleaved burst types, and a
full page burst is available for the sequential burst mode. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, aas unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst will wrap within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A2-A8 (each x16)
when the burst length is set to four; and by A3-A8 (each x16)
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within the
page if the boundary is reached.
The normal operating mode is selected by setting M7 and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and
WRITE bursts.
Test Modes and reserved states should not be used
because unknown operation or incompatibility with future
version may result.
Write Burst Mode
When M9=0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9=1,
the programmed burst length applies to READ bursts, but
WRITE accesses are single-location (non-burst) accesses.
Command Inhibit
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of first
valid data presented on the Output bus (DQ0-DQ79). The
latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
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No Operation (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS\ is
LOW). This prevents unwanted commands from being
registered during IDLE or WAIT states. Operations
already in progress are not affected.
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Load Mode Register
The MODE REGISTER is loaded via inputs A0-A11 (A12
should be driven LOW). See MODE REGISTER heading in
the REGISTER DEFINITION section. The LOAD MODE
REGISTER command can only be issued when all banks are
idle, and a subsequent executable command cannot be issued
until tMRD is met.
HIGH, the corresponding data inputs will be ignored, and
a WRITE will not be executed to that byte/column
location.
Precharge
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row
access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be PRECHARGED, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care”. Once a bank has been PRECHARGED, it
is in the idle state and must be activated prior to any
READ or WRITE commands being issued to that bank.
Active
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A12 selects the row. This row remains active
(or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
Auto Precharge
AUTO PRECHARGE is a feature which performs the
same individual bank PRECHARGE function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable AUTO
PRECHARGE in conjunction with a specific READ or
WRITE command. A PRECHARGE of the bank/row that
is addressed with the READ or WRITE command is
automatically performed upon completion of the READ
or WRITE burst, except in the full-page burst mode,
where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE
command.
AUTO PRECHARGE ensures that the PRECHARGE is
initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank until
the PRECHARGE time (tRP) is completed. This is
determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each
burst type Operation.
Read
The read command is used to initiate a burst read access to an
active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-A8 (each x16)
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row will remain open
for subsequent accesses. READ data appears on the DQs
subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the
corresponding DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide valid
data.
Write
The WRITE command is used to initiate a BURST WRITE
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A8
(each x16) selects the starting column location. The value on
input A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be PRECHARGED at the end of the WRITE
BURST; if for subsequent accesses input data appearing on
the DQs is WRITTEN to the memory array subject to the
DQM input logic level appearing coincident with the data. If
a given DQM signal is registered LOW, the corresponding
data will be written to memory; if the DQM signal is
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Burst Terminate
The BURST TERMINATE command is used to truncate
either a fixed-length or full-page burst. The most recently
registered READ or WRITE command prior to the
BURST TERMINATE command will be truncated.
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Auto Refresh
AUTO REFRESH is used during normal operation of the
SDRAM MCP and is analogous to CAS\-BEFORE-RAS\
(CBR) REFRESH in conventional DRAMs. This command is
non-persistent, so it must be issued each time a refresh is
required. All active banks must be PRECHARGED prior to
issuing an AUTO REFRESH command. The AUTO
REFRESH command should not be issued until the minimum
tRP has been met after the PRECHARGE command.
The addressing is generated by the internal REFRESH
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. The 256Mb SDRAM MCP
requires 8,192 AUTO REFRESH cycles every 64ms (tREF).
Providing a distributed AUTO REFRESH command every
7.81us will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(tRFC), once every 64ms.
Upon exiting the SELF REFRESH mode, AUTO
REFRESH commands must be issued every 7.81us or less
as both SELF REFRESH and AUTO REFRESH utilize
the row refresh counter.
Self Refresh
The SELF REFRESH command can be used to retain data in
the SDRAM MCP, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM MCP
retains data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM MCP
become “Don’t Care” with the exception of CKE, which must
remain LOW.
Once self refresh mode is engaged, the SDRAM provides its
own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM MCP must remain in SELF
REFRESH mode for a minimum period equal to tRAS and
may remain in SELF REFRESH for an indefinite period of
time beyond the minimum.
The procedure for exiting SELF REFRESH requires a
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH.
Once CKE is HIGH, the SDRAM MCP must have NOP
commands issued (a minimum of two clocks) for tXSR
because time is required for the completion of any internal
REFRESH in progress.
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