SGRAM MODULE
KMM965G256BQ(P)N / KMM966G256BQ(P)N
2MB SGRAM MODULE
(256Kx64 SODIMM based on 256Kx32 SGRAM)
Unbuffered SGRAM
Graphics
64-bit Non-ECC/Parity
144-pin SODIMM
Revision 2.5
July 1998
-1-
Rev. 2.5 (Jul. 1998)
SGRAM MODULE
Revision History
Revision 2.5 (July 1998)
KMM965G256BQ(P)N / KMM966G256BQ(P)N
• Added -7(143MHz) speed product.
• Changed SPD data, Byte #62 from 02h to 00h.
Revision 2.4 (June 1998)
• Added KMM965G256B product which does not support SPD.
Revision 2.3 (March 1998)
• Changed the Current values of ICC1, ICC3N, ICC4, ICC7 in
DC CHARACTERISTICS.
Revision 2.2 (February 1998)
• Removed KMM966G256B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).
• Changed the Current values of ICC1, ICC4, ICC5, ICC6, ICC7 in
DC CHARACTERISTICS.
• Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in
AC PARAMETER.
• Changed SPD data according to each changed AC Parameters.
• Delete a page including
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 2.1 (December 3, 1997)
• Modified an erratum pin name of Pin #65 from CS1 to CS1, Pin #66 from CS0 to CS0, Pin #94 from ADD to VDD in
PIN
CONFIGURATIONS
- page 3.
Revision 2.0 (November 26, 1997)
• Initial Draft --- Final Spec. (comply with Intel 0.2 spec. which is basically compatible with Intel 0.1 spec. except the
changed functionality of
Strapping Resistor
DQ31 from Memory Timing to CAS Latency - page 4.
-2-
Rev. 2.5 (Jul. 1998)
SGRAM MODULE
KMM965G256BQ(P)N / KMM966G256BQ(P)N
KMM965G256BQ(P)N / KMM966G256BQ(P)N SGRAM SODIMM
256Kx64 SGRAM SODIMM based on 256Kx32, 1K Refresh, 3.3V Synchronous Graphic RAMs
GENERAL DESCRIPTION
The Samsung KMM965(6)G256BQ(P)N is a 256K bit x 64
Synchronous Graphic RAM high density memory module. The
Samsung KMM965(6)G256BQ(P)N consists of two CMOS
256K x 32 bit Synchronous Graphic RAMs in 100pin QFP
packages mounted on a 144pin glass-epoxy substrate. Five
0.1uF decoupling capacitors are mounted on the printed circuit
board for each Synchronous GRAM.
The KMM965(6)G256BQ(P)N is a Small Outline Dual In-line
Memory Module and is intended for mounting into 144-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
•
•
•
•
•
•
•
•
•
•
•
FEATURE
• Performance range
Part NO.
KMM965(6)G256BQ(P)N-G7
KMM965(6)G256BQ(P)N-G8
KMM965(6)G256BQ(P)N-G0
Max. Freq. (t
CC
)
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
100MHz (10ns) @CL=3
* KM965(6)G256BQN : based on PQFP Component
KM965(6)G256BPN : based on TQFP Component
Burst Mode Operation
BLOCK-WRITE and Write-per-bit capability
Independent byte operation via DQM0 ~ 7
Auto & Self Refresh Capability (1024 cycles / 16ms)
LVTTL compatible inputs and outputs
Single 3.3V
±0.3V
power supply
MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Optional Serial PD with EEPROM(KMM966G256B)
Resistor Strapping Options for speed and CAS Latency
PCB : Height(1000mil
),
single sided components
PIN CONFIGURATIONS (Front Side / Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ63
DQ61
DQ59
DQ57
V
DD
DQ55
DQ53
DQ51
DQ49
V
SS
DQM7
DQM5
V
DD
DQ47
DQ45
DQ43
DQ41
V
SS
DQ39
DQ37
DQ34
DQ33
V
DD
RSVD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ62
DQ60
DQ58
DQ56
V
DD
DQ54
DQ52
DQ50
DQ48
V
SS
DQM6
DQM4
V
DD
DQ46
DQ44
DQ42
DQ40
V
SS
DQ38
DQ36
DQ34
DQ32
V
DD
RSVD
Pin
Front
Pin
Back
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ31
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
DQ17
V
DD
DQM3
DQM1
V
SS
DQ15
DQ13
DQ11
DQ9
V
DD
DQ7
DQ5
DQ3
DQ1
V
SS
**SDA
V
DD
Pin
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ30
DQ28
DQ26
DQ24
V
SS
DQ22
DQ20
DQ18
DQ16
V
DD
DQM2
DQM0
V
SS
DQ14
DQ12
DQ10
DQ8
V
DD
DQ6
DQ4
DQ2
DQ0
V
SS
**SCL
V
DD
PIN NAMES
Pin Name
A0 ~ A8
BA(A9)
DQ0 ~ 63
CLK0, *CLK1
CKE
CS0, *CS1
RAS
CAS
WE
DSF
DQM0 ~ 7
V
DD
V
SS
**SDA
**SBA
**SCL
RSVD
RFU
NC
Function
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Define Special Function
DQM
Power Supply (3.3V)
Ground
Serial Address Data I/O
EEPROM Device Address
Serial Clock
Reserved
Reserved for future use
No Connection
Voltage Key
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
RSVD
RSVD
V
SS
DSF
RFU
RFU
V
DD
CS1
RAS
WE
V
SS
CLK1
V
DD
RSVD
RSVD
(A11)
BA(A9)
A7
V
SS
A5
A3
A1
V
DD
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
RSVD
RSVD
V
SS
RFU
RFU
**SBA
V
DD
CS0
CAS
CKE
V
SS
CLK0
V
DD
RSVD
RSVD
(A10)
A8/AP
A6
V
SS
A4
A2
A0
V
DD
*
These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
-3-
Rev. 2.5 (Jul. 1998)
SGRAM MODULE
Pin
CLK
CS
Name
System Clock
Chip Select
KMM965G256BQ(P)N / KMM966G256BQ(P)N
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
Enables row access & precharge.
RAS low.
CAS low.
PIN CONFIGURATION DESCRIPTION
CKE
Clock Enable
A0 ~ A8
BA(A9)
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
DSF
V
DD
/V
SS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply/Ground
Latches column addresses on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power and ground for the input buffers and the core logic.
RESISTOR STRAPPING OPTIONS
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled
AC CHARATERISTICS.
Clock Frequency and Memory Timing
Cycle Time
10 ns
8ns
7ns
DQ30
1
1
0
DQ29
0
1
0
CAS Latency
CAS Latency
3
2 and 3
DQ31
0
1
-4-
Rev. 2.5 (Jul. 1998)
SGRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
KMM965G256BQ(P)N / KMM966G256BQ(P)N
CS0
•
DQM0
DQ0
DQ7
DQM1
DQ8
•
•
•
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
DQM4
DQ32
U0
DQ39
DQM5
DQ40
•
•
•
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
U1
DQ15
DQM2
DQ16
•
•
•
•
•
•
DQ47
DQM6
DQ48
•
•
•
DQ23
DQM3
DQ24
DQ55
DQM7
DQ56
•
•
•
DQ31
•
•
•
•
•
•
DQ63
CKE
RAS
CAS
WE
DSF
A(8:0)
BA(A9)
U0 to U1
U0 to U1
U0 to U1
U0 to U1
U0 to U1
U0 to U1
U0 to U1
0Ω
CLK0
U0, U1
Serial PD
SCL
A0
V
DD
Vss
•
•
•
•
•
•
Five 0.1uF Capacitors
per SGRAM device
To all SGRAMs
A1
A2
•
SBA
V
SS
SDA
.
.
.
* Serial PD is optional
-5-
Rev. 2.5 (Jul. 1998)
DSP 与 ARM 处理器
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