Philips Semiconductors
Product specification
1-of-2 non-inverting demultiplexer with
3-state deselected output
FEATURES
•
Wide supply voltage range from 1.65 to 5.5 V
•
5 V tolerant input/output for interfacing with 5 V logic
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
•
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance exceeds 250 mA
•
Direct interface with TTL levels
•
SOT363 and SOT457 package
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay input A to output nY
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
74LVC1G18
The 74LVC1G18 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 or 5 V devices. These
features allow the use of these devices in a mixed
3.3 and 5 V environment.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer
with a 3-state output. The 74LVC1G18 buffers the data on
input pin A and passes it either to output 1Y or 2Y,
depending on whether the state of the select input (pin S)
is LOW or HIGH.
TYPICAL
5.1
3.2
3.2
3.0
2.3
2.5
28.8
ns
ns
ns
ns
ns
UNIT
pF
pF
2003 Jul 25
2
Philips Semiconductors
Product specification
1-of-2 non-inverting demultiplexer with
3-state deselected output
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
PARAMETER
supply voltage
input voltage
output voltage
active mode
V
CC
= 0 V; Power-down or
high-impedance state
T
amb
t
r
, t
f
operating ambient temperature
input rise and fall times
V
CC
= 1.65 to 2.7 V
V
CC
= 2.7 to 5.5 V
CONDITIONS
0
0
0
−40
0
0
MIN.
1.65
74LVC1G18
MAX.
5.5
5.5
V
CC
5.5
+125
20
10
V
V
V
V
UNIT
°C
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation
T
amb
=
−40
to +125
°C
V
I
< 0
note 1
V
O
> V
CC
or V
O
< 0
active mode; notes 1 and 2
V
O
= 0 to V
CC
CONDITIONS
−
−0.5
−
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
+6.5
±50
±100
+150
300
V
mA
V
mA
V
mA
mA
°C
mW
UNIT
V
CC
+ 0.5 V
Power-down mode; notes 1 and 2
−0.5
2003 Jul 25
4
Philips Semiconductors
Product specification
1-of-2 non-inverting demultiplexer with
3-state deselected output
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
OTHER
T
amb
=
−40
to +85
°C;
note 1
V
IH
HIGH-level input voltage
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
V
IL
LOW-level input voltage
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
V
OL
LOW-level output voltage V
I
= V
IH
or V
IL
I
O
= 100
µA
I
O
= 4 mA
I
O
= 8 mA
I
O
= 12 mA
I
O
= 24 mA
I
O
= 32 mA
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA
I
O
=
−4
mA
I
O
=
−8
mA
I
O
=
−12
mA
I
O
=
−24
mA
I
O
=
−32
mA
I
LI
I
OZ
I
off
I
CC
∆I
CC
input leakage current
V
I
= 5.5 V or GND
3-state output OFF-state V
I
= V
IH
or V
IL
;
current
V
O
= V
CC
or GND
power OFF leakage
current
V
I
or V
O
= 5.5 V
1.65 to 5.5
1.65
2.3
2.7
3.0
4.5
5.5
5.5
0
5.5
2.3 to 5.5
V
CC
−
0.1
1.2
1.9
2.2
2.3
3.8
−
−
−
−
−
−
−
−
−
−
−
±0.1
±0.1
±0.1
0.1
5
1.65 to 5.5
1.65
2.3
2.7
3.0
4.5
−
−
−
−
−
−
−
−
−
−
−
−
0.65
×
V
CC
1.7
2.0
0.7
×
V
CC
−
−
−
−
−
−
−
−
−
−
−
−
V
CC
(V)
MIN.
TYP.
74LVC1G18
MAX.
UNIT
−
−
−
−
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
0.1
0.45
0.3
0.4
0.55
0.55
−
−
−
−
−
−
±5
±10
±10
10
500
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
quiescent supply current V
I
= V
CC
or GND;
I
O
= 0
additional quiescent
supply current per pin
V
I
= V
CC
−
0.6 V;
I
O
= 0
2003 Jul 25
5
测试/测量
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