2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
FEATURES:
• Organized as 256K x8 Flash + 128K x8 SRAM
• Single 3.0-3.6V Read and Write Operations
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 10 mA (typical) for Flash
and 20 mA (typical) for SRAM Read
– Standby Current: 10 µA (typical)
• Flash Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Times:
– Flash: 300 ns
– SRAM: 300 ns
PRODUCT DESCRIPTION
The SST31LF021E device is a 256K x8 CMOS flash
memory bank combined with a 128K x8 CMOS SRAM
memory bank manufactured with SST’s proprietary, high
performance SuperFlash technology. Two pinout stan-
dards are available for this device. The SST31LF021E
conforms to standard EPROM pinouts. The
SST31LF021E device writes (SRAM or flash) with a 3.0-
3.6V power supply. The monolithic SST31LF021E de-
vice conforms to Software Data Protect (SDP) com-
mands for x8 EEPROMs.
Featuring high performance Byte-Program, the flash
memory bank provides a maximum Byte-Program time
of 20 µsec. The entire flash memory bank can be erased
and programmed byte-by-byte in typically 4 seconds,
when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program
operation. To protect against inadvertent flash write, the
SST31LF021E device has on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, the
SST31LF021E device is offered with a guaranteed en-
durance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST31LF021E operates as two independent
memory banks with respective bank enable signals. The
SRAM and Flash memory banks are superimposed in
the same memory address space. Both memory banks
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
•
•
Latched Address and Data for Flash
Flash Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Bank-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Bank Rewrite Time: 4 seconds (typical)
Flash Automatic Erase and Program Timing
– Internal V
PP
Generation
Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
– 32-Pin TSOP (8mm x 13.4mm)
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•
•
•
•
•
enable signals. The SRAM bank enable signal, BES#
selects the SRAM bank and the flash memory bank
enable signal, BEF# selects the flash memory bank. The
WE# signal has to be used with Software Data Protec-
tion (SDP) command sequence when controlling the
Erase and Program operations in the flash memory
bank. The SDP command sequence protects the data
stored in the flash memory bank from accidental alter-
ation.
The SST31LF021E provides the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Byte-Program concurrently. All
flash memory Erase and Program operations will auto-
matically latch the input address and data signals and
complete the operation in background without further
input stimulus requirement. Once the internally con-
trolled Erase or Program cycle in the flash bank has
commenced, the SRAM bank can be accessed for Read
or Write.
The SST31LF021E device is suited for applications that
use both nonvolatile flash memory and volatile SRAM
memory to store code or data. For all system applica-
tions, the SST31LF021E device significantly improves
performance and reliability, while lowering power con-
sumption, when compared with multiple chip solutions.
The SST31LF021E inherently uses less energy during
Erase and Program than alternative flash technologies.
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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of
Silicon Storage Technology, Inc. These specifications are subject to change without notice.
1
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
When programming a flash device, the total energy
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter Erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies. The monolithic
ComboMemory eliminates redundant functions when
using two separate memories of similar architecture;
therefore, reducing the total power consumption.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase with
accumulated Erase/Program cycles.
The SST31LF021E device also improves flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate de-
vices. To meet high density, surface mount require-
ments, the SST31LF021E device is offered in 32-pin
TSOP packages. See Figure 1 for the pinouts.
Device Operation
The ComboMemory uses BES# and BEF# to control
operation of either the SRAM or the flash memory bank.
Bus contention is eliminated as the monolithic device will
not recognize both bank enables as being simulta-
neously active. If both bank enables are asserted (i.e.,
BEF# and BES# are both low), the BEF# will dominate
while the BES# is ignored and the appropriate operation
will be executed in the flash memory bank. SST does not
recommend that both bank enables be simultaneously
asserted. All other address, data, and control lines are
shared; which minimizes power consumption and area.
The device goes into standby when both bank enables
are raised to V
IHC
.
SRAM Operation
With BES# low and BEF# high, the SST31LF021E
operate as a 128K x8 CMOS SRAM, with fully static
operation requiring no external clocks or timing strobes.
The SRAM is mapped into the first 128 KByte address
space of the device. Read and Write cycle times are
equal.
SRAM Read
The SRAM Read operation of the SST31LF021E is
controlled by OE# and BES#, both have to be low with
WE# high, for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. When BES# and
BEF# are high, both memory banks are deselected. OE#
is the output control and is used to gate data from the
output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing
diagram, Figure 2, for further details.
SRAM Write
The SRAM Write operation of the SST31LF021E is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. BES# is used for SRAM
bank selection. During the Byte-Write operation, the
addresses and data are referenced to the rising edge of
either BES# or WE#, whichever occurs first. The Write
time is measured from the last falling edge to the first
rising edge of BES# and WE#. Refer to the Write cycle
timing diagram, Figure 3, for further details.
Flash Operation
With BEF# active, the SST31LF021E operates as a
256K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with
the JEDEC standard SDP command sequences. Ad-
dress and data are latched during the SDP commands
and internally timed Erase and Program operations.
Flash Read
The Read operation of the SST31LF021E device is
controlled by BEF# and OE#, both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram (Figure 4) for
further details.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory
bank Program and Erase operations of the
SST31LF021E. SDP commands are loaded to the flash
memory bank using standard microprocessor write se-
quences. A command is loaded by asserting WE# low
while keeping BEF# low and OE# high. The address is
latched on the falling edge of WE# or BEF#, whichever
occurs last. The data is latched on the rising edge of WE#
or BEF#, whichever occurs first.
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
2
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Flash Byte-Program Operation
The flash memory bank of the SST31LF021E device is
programmed on a byte-by-byte basis. The Program
operation consists of three steps. The first step is the
three-byte-load sequence for Software Data Protection.
The second step is to load byte address and byte data.
During the Byte-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the rising
edge of either BEF# or WE#, whichever occurs first. The
third step is the internal Program operation which is
initiated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 5
and 6 for WE# and BEF# controlled Program operation
timing diagrams and Figure 16 for flowcharts. During the
Program operation, the only valid Flash Read operations
are Data# Polling and Toggle Bit. During the internal
Program operation, the host is free to perform additional
tasks. Any SDP commands loaded during the internal
Program operation will be ignored.
Flash Sector-Erase Operation
The Sector-Erase operation allows the system to erase
the flash memory bank on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4
KBytes. The Sector-Erase operation is initiated by ex-
ecuting a six-byte-command load sequence for Software
Data Protection with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address
lines A17-A12 will be used to determine the sector
address. The sector address is latched on the falling edge
of the sixth WE# pulse, while the command (30H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any SDP commands loaded during the
Sector-Erase operation will be ignored.
Flash Bank-Erase Operation
The SST31LF021E flash memory bank provides a Bank-
Erase operation, which allows the user to erase the entire
flash memory bank array to the “1’s” state. This is useful
when the entire bank must be quickly erased. The Bank-
Erase operation is initiated by executing a six-byte
Software Data Protection command sequence with Bank-
Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or BEF# pulse, which-
ever occurs first. During the internal Erase operation, the
only valid Flash Read operations are Toggle Bit and
Data# Polling. See Table 4 for the command sequence,
© 2000 Silicon Storage Technology, Inc.
Figure 10 for timing diagram, and Figure 19 for the
flowchart. Any SDP commands loaded during the Bank-
Erase operation will be ignored.
Flash Write Operation Status Detection
The SST31LF021E flash memory bank provides two
software means to detect the completion of a flash
memory bank Write (Program or Erase) cycle, in order to
optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7)
and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates
the internal Program or Erase operation. The actual
completion of the nonvolatile write is asynchronous with
the system; therefore, either a Data# Polling or Toggle Bit
Read may be simultaneous with the completion of the
Write cycle. If this occurs, the system may possibly get
an erroneous result, i.e., valid data may appear to conflict
with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed
location an additional two (2) times. If both reads are
valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Flash Data# Polling (DQ7)
When the SST31LF021E flash memory bank is in the
internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. The flash memory bank is then ready for the next
operation. During internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase
operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operation. For Sector
or Bank-Erase, the Data# Polling is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 17 for a flow-
chart.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any
consecutive attempts to read DQ6 will produce alternat-
ing 0’s and 1’s, i.e., toggling between 0 and 1. When the
internal Program or Erase operation is completed, the
toggling will stop. The flash memory bank is then ready
for the next operation. The Toggle Bit is valid after the
rising edge of the fourth WE# (or BE#) pulse for Program
operation. For Sector or Bank-Erase, the Toggle Bit is
valid after the rising edge of the sixth WE# (or BEF#)
pulse. See Figure 8 for Toggle Bit timing diagram and
Figure 17 for a flowchart.
371-02 2/00
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3
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Flash Memory Data Protection
The SST31LF021E flash memory bank provides both
hardware and software features to protect nonvolatile
data from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less
than 5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST31LF021E provides the JEDEC approved Soft-
ware Data Protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase opera-
tion requires the inclusion of six-byte load sequence. The
SST31LF021E device is shipped with the Software Data
Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP com-
mand sequence, invalid SDP commands will abort the
device to the Read mode, within TRC.
Concurrent Read and Write Operations
The SST31LF021E provides the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the Flash. The device will ignore
all SDP commands when an Erase or Program operation
is in progress. This allows data alteration code to be
executed from SRAM, while altering the data in Flash.
The following table lists all valid states. SST does not
recommend that both bank enables, BEF# and BES#, be
simultaneously asserted.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
Product Identification
The product identification mode identifies the device as
the SST31LF021E and manufacturer as SST. This mode
may be accessed by hardware or software operations.
The hardware device ID Read operation is typically used
by a programmer to identify the correct algorithm for the
SST31LF021E flash memory bank. Users may wish to
use the software product identification operation to iden-
tify the part (i.e., using the device code) when using
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the software ID entry
and read timing diagram and Figure 18 for the ID entry
command sequence flowchart.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Address
Manufacturer’s Code
SST31LF021E Device Code
0000H
0001H
Data
BF H
19 H
371 PGM T1.0
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the
Software Product Identification mode must be exited.
Exiting is accomplished by issuing the Exit ID command
sequence, which returns the device to the Read opera-
tion. Please note that the software-reset command is
ignored during an internal Program or Erase operation.
See Table 4 for software command codes, Figure 12 for
timing waveform and Figure 18 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic
capacitor to be placed as close as possible between V
DD
and V
SS
, e.g., less than 1 cm away from the V
DD
pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from V
DD
to V
SS
should be placed within 1 cm
of the V
DD
pin.
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
© 2000 Silicon Storage Technology, Inc.
4
371-02 2/00
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
F
UNCTIONAL
B
LOCK
D
IAGRAM OF
SST31LF021E
1,048,576 bit
SRAM
Cell Array
1
2
Address Buffers
AMS - A0
BES#
BEF#
OE#
WE#
Control Logic
I/O Buffers
DQ7 - DQ0
3
4
Address Buffers
& Latches
2,097,152 bit
EEPROM
Cell Array
371 ILL B1.1
Note: AMS = Most Significant Address
5
6
A11
A9
A8
A13
A14
A17
BES#
VDD
WE#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
371 ILL F01.0
OE#
A10
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
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8
9
10
11
F
IGURE
1: P
IN
A
SSIGNMENTS FOR
32-
PIN
TSOP (8mm x 13.4mm)
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13
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© 2000 Silicon Storage Technology, Inc.
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371-02 2/00
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