32 Mbit (x16) Multi-Purpose Flash
SST39VF320
SST39VF3202.7V 32Mb (x16) MPF memory
Preliminary Specifications
FEATURES:
• Organized as 2M x16
• Single 2.7-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 70 ns
– 90 ns
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
– Chip Rewrite Time:
15 seconds (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST39VF320 devices are 2M x16 CMOS Multi-Pur-
pose Flash (MPF) manufactured with SST's proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39VF320 write (Program or
Erase) with a 2.7-3.6V power supply.
Featuring high performance Word-Program, the
SST39VF320 devices provide a typical Word-Program
time of 7 µsec. The devices use Toggle Bit or Data# Polling
to indicate the completion of Program operation. To protect
against inadvertent write, these devices have on-chip hard-
ware and software data protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, the SST39VF320 are offered with a guaranteed typi-
cal endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39VF320 devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
the SST39VF320 significantly improve performance and
reliability, while lowering power consumption. The
SST39VF320 inherently use less energy during Erase and
Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
1
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies. The devices also improve
flexibility while lowering the cost for program, data, and con-
figuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39VF320 is offered in 48-lead TSOP and 48-ball
TFBGA packages. See Figures 1 and 2 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
32 Mbit Multi-Purpose Flash
SST39VF320
Preliminary Specifications
The SST39VF320 also have the
Auto Low Power
mode
which puts the device in a near standby mode after data
has been accessed with a valid Read operation. This
reduces the I
DD
active read current from typically 9 mA to
typically 3 µA. The Auto Low Power mode reduces the typi-
cal I
DD
active read current to the range of 2 mA/MHz of
read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto Low
Power mode after power-up with CE# held steadily low until
the first address transition or CE# is driven high.
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
Read
The Read operation of the SST39VF320 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST39VF320 provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39VF320 are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 10
µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 16 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored.
Write Operation Status Detection
The SST39VF320 provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF320 offer both Sector-Erase
and Block-Erase modes. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
©2003 Silicon Storage Technology, Inc.
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2
32 Mbit Multi-Purpose Flash
SST39VF320
Preliminary Specifications
Data# Polling (DQ
7
)
When the SST39VF320 are in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. Note that even though DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
timing diagram and Figure 17 for a flowchart.
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion
of six-byte sequence. This group of devices are shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes.
During SDP command sequence, invalid commands will
abort the device to Read mode within T
RC
. The contents of
DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other value, during any
SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF320 also contain the CFI information to
describe the characteristics of the device. In order to
enter the CFI Query mode, the system must load the
three-byte sequence, similar to the Software ID Entry com-
mand. The last byte cycle of this command loads 98H (CFI
Query command) to address 5555H. Once the device
enters the CFI Query mode, the system can read CFI
data at the addresses given in Tables 5 through 7. The
system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF320 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table
4 for software operation, Figure 11 for the Software ID
Entry and Read timing diagram, and Figure 18 for the
Software ID Entry command sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST39VF320
0001H
2783H
T1.1 1143
Data Protection
The SST39VF320 provide both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Data
00BFH
0000H
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
S71143-02-000
11/03
Software Data Protection (SDP)
The SST39VF320 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration oper-
ations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
©2003 Silicon Storage Technology, Inc.
3
32 Mbit Multi-Purpose Flash
SST39VF320
Preliminary Specifications
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform, and Figure 18 for a
flowchart.
F
UNCTIONAL
B
LOCK
D
IAGRAM
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
DQ15 - DQ0
1143 B1.1
Control Logic
I/O Buffers and Data Latches
SST39VF320
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SST39VF320
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Standard Pinout
Top View
Die Up
SST39VF320
1143 48-tsop EK P01.10
FIGURE 1: P
IN
A
SSIGNMENTS FOR
48-
LEAD
TSOP
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
4
32 Mbit Multi-Purpose Flash
SST39VF320
Preliminary Specifications
TOP VIEW (balls facing down)
SST39VF320
6
5
4
3
2
1
A13
A9
WE#
NC
A7
A3
A12
A8
NC
NC
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
NC
DQ15 VSS
DQ7 DQ14 DQ13 DQ6
DQ5 DQ12 VDD DQ4
DQ2 DQ10 DQ11 DQ3
DQ0 DQ8 DQ9 DQ1
A0
CE#
OE# VSS
1143
48-tfbga B3K P02a.3
A
B
C
D
E
F
G
H
FIGURE 2: P
IN
A
SSIGNMENTS FOR
48-
BALL
TFBGA
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
20
-A
0
DQ
15
-DQ
0
Pin Name
Address Inputs
Data Input/output
Functions
To provide memory addresses. During Sector-Erase A
20
-A
11
address lines will select the
sector. During Block-Erase A
20
-A
15
address lines will select the block.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
Unconnected pins.
T2.2 1143
CE#
OE#
WE#
V
DD
V
SS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
2.7-3.6V for SST39VF320
TABLE 3: O
PERATION
M
ODES
S
ELECTION
Mode
Read
Program
Erase
Standby
Write Inhibit
Product Identification
Software Mode
V
IL
V
IL
V
IH
See Table 4
T3.1 1143
CE#
V
IL
V
IL
V
IL
V
IH
X
X
OE#
V
IL
V
IH
V
IH
X
V
IL
X
WE#
V
IH
V
IL
V
IL
X
X
V
IH
DQ
D
OUT
D
IN
X
1
High Z
High Z/ D
OUT
High Z/ D
OUT
Address
A
IN
A
IN
Sector or Block address,
XXH for Chip-Erase
X
X
X
1. X can be V
IL
or V
IH
, but no other value
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
5
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