4 Mbit (x16) Multi-Purpose Flash
SST39WF400A
SST39WF400A1.8V 4Mb (x16) MPF memory
Data Sheet
FEATURES:
• Organized as 256K x16
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 90 ns
– 100 ns
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-bump XFLGA (4mm x 6mm) Micro-Package
PRODUCT DESCRIPTION
The SST39WF400A device is a 256K x16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39WF400A writes (Pro-
gram or Erase) with a 1.65-1.95V power supply. This
device conforms to JEDEC standard pin assignments for
x16 memories.
Featuring
high-performance
Word-Program,
the
SST39WF400A device provides a typical Word-Program
time of 28 µsec. The device uses Toggle Bit or Data# Poll-
ing to detect the completion of the Program or Erase opera-
tion. To protect against inadvertent writes, it has on-chip
hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, this device is offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39WF400A device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
it significantly improves performance and reliability, while
lowering power consumption. It inherently uses less energy
©2004 Silicon Storage Technology, Inc.
S71220-05-000
6/04
1
during Erase and Program than alternative flash technolo-
gies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39WF400A
is offered in both a 48-ball TFBGA package and 48-ball
Micro-Packages. See Figures 1 and 2 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39WF400A is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39WF400A provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39WF400A is programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 40
µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 16 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored.
Write Operation Status Detection
The SST39WF400A provides two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile Write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both Reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39WF400A offers both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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2
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Data# Polling (DQ
7
)
When the SST39WF400A is in the internal Program oper-
ation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is completed, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Software Data Protection (SDP)
The SST39WF400A provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within T
RC
. The contents of DQ
15
-
DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
The SST39WF400A also contains the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
Data Protection
The SST39WF400A provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2004 Silicon Storage Technology, Inc.
S71220-05-000
6/04
3
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Product Identification
The Product Identification mode identifies the devices as
the SST39WF400A and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table 4
for software operation, Figure 11 for the Software ID Entry
and Read timing diagram, and Figure 18 for the Software
ID Entry command sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
T
ABLE
Address
Manufacturer’s ID
Device ID
SST39WF400A
0001H
272FH
T1.0 1220
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform, and Figure 18 for a
flowchart.
Data
00BFH
0000H
F
UNCTIONAL
B
LOCK
D
IAGRAM
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
DQ15 - DQ0
1220 B1.0
Control Logic
I/O Buffers and Data Latches
©2004 Silicon Storage Technology, Inc.
S71220-05-000
6/04
4
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TOP VIEW (balls facing down)
SST39WF400A
6
A13
A12 A14 A15 A16
A8
NC
NC
A17
A4
5
A9
NC DQ15 V
SS
A10 A11 DQ7 DQ14 DQ13 DQ6
NC
NC
A6
A2
NC DQ5 DQ12 VDD DQ4
1220 48-tfbga P01.0
4
WE#
3
NC
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0
CE# OE# V
SS
2
A7
1
A3
A
B
C
D
E
F
G
H
FIGURE 1: P
IN
A
SSIGNMENTS FOR
48-
BALL
TFBGA
TOP VIEW (balls facing down)
SST39WF400A
6
A2
A4
A3
A5
A6
A7
NC
A17
NC
NC
NC
WE#
NC
NC
A9
A10
A8
A11
A13
A12
A14
A15
1220 48-wfbga-xflga P03_4.0
5
A1
4
A0
3
CE#
DQ8 DQ10
OE# DQ9
NC
NC
DQ4 DQ11 A16
DQ5 DQ6 DQ7
2
V
SS
1
DQ0 DQ1 DQ2 DQ3
V
DD
DQ12 DQ13 DQ14 DQ15 V
SS
A
B
C
D
E
F
G
H
J
K
L
FIGURE 2: P
IN
A
SSIGNMENTS FOR
48-
BALL
WFBGA
AND
48-
BUMP
XFLGA
©2004 Silicon Storage Technology, Inc.
S71220-05-000
6/04
5
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