Envoy
™
-8FE Device
Octal Fast Ethernet Controller
TXC-06840
DATA SHEET
PRODUCT PREVIEW
FEATURES
• 8 Independent SMII ports operating at 10/100
Mbit/s mixed mode
• 8 IEEE 802.3 compliant Media Access Controllers
(MACs) each connected to an SMII port
• POS-PHY Level 2 interface operating at 50 MHz
• OIF SPI-3 interface operating at 100 MHz
• Full-Duplex and Half-Duplex (CSMA/CD)
operation per MAC
• Support for VLAN tagged frames
• Automatic PAUSE Frame Generation and
Termination
• Ingress and Egress FIFOs on a per MAC basis
guarantee loss-less transmission
• Programmable High and Low FIFO watermarks for
space and frame availability signal generation
• Programmable frame length
• Programmable Inter-Packet Gap (IPG) between
Ethernet Frames
• Frame integrity verification (FCS and length
checks)
• Statistics and performance monitoring support for
RMON
• Far end switch side loopback for diagnostics
• 32-bit Motorola host interface, operating at 33/50
MHz
• IEEE 1149.1 JTAG support
• 1.8V core and 3.3V I/O power supplies, 5V tolerant
I/O leads
• Industrial Temperature Range (-40
°
C to +85
°
C)
• 376-lead plastic ball grid array (PBGA) package,
23 mm x 23 mm
DESCRIPTION
The Envoy
™
-8FE is an Octal Fast Ethernet to POS-PHY
Level 2/SPI-3 controller. Each SMII port is connected to a
Media Access Controller (MAC), operating at 10/100
Mbits/s mixed mode. The MAC is programmable to pro-
vide Full-Duplex or Half-Duplex operation. The
Envoy-8FE bridges the gap between POS-PHY Level 2
and OIF SPI-3 standard technology used in telecom to
cost effective standards based Ethernet technologies.
Additionally, the Envoy-8FE is a cost-effective single chip
solution for backplane switching and physical layer appli-
cations, such as Ethernet over VDSL and Ethernet
uplinks, utilizing state of the art congestion control man-
agement and flow control mechanisms to provide carrier
class reliability.
The Envoy-8FE is designed to interface directly with
POS-PHY Level 2/SPI-3 compliant devices, including
standard off the shelf network processors. On the Ether-
net side, the Envoy-8FE interfaces directly with standard
Fast Ethernet PHY devices via the Serial Media Indepen-
dent Interface (SMII) at 125 MHz. The Envoy-8FE has on-
chip buffering and provides backpressure support in both
the ingress and egress directions.
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APPLICATIONS
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NETWORK SIDE
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+1.8v
+3.3v
JTAG
Ethernet
Motorola Management
Host Interface Interface
SWITCH SIDE
10/100 Mbit/s SMII
(Port 0)
Envoy-8FE
Octal Fast Ethernet
Controller
POS-PHY Level 2
or
OIF SPI-3
10/100 Mbit/s SMII
(Port 7)
TXC-06840
U.S. and/or foreign patents issued or pending
Copyright © 2003 TranSwitch Corporation
Envoy is a trademark of TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
PRODUCT PREVIEW
TXC-06840-MB
Ed. 1, January 2003
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, Connecticut 06484
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
•
USA
PRODUCT PREVIEW
information documents contain information on
products in their formative or design phase of development. Features,
characteristic data and other specifications are subject to change. Contact
TranSwitch Applications Engineering for current information on this product.
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3G Wireless Radio Network Controllers (RNCs)
3G Wireless Base Stations
Multi-service Switches
IP DSLAMs
Edge Routers
Interconnect for Fast Ethernet Backplanes
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-8FE
TXC-06840
TABLE OF CONTENTS
Section
Page
List of Figures .................................................................................................................................... 3
Features............................................................................................................................................. 4
10/100 Mbit/s Media Access Controller (MAC) Block .................................................................. 4
Serial Media Independent Interface (SMII) .................................................................................. 4
POS-PHY Level 2/SPI-3 Interface ............................................................................................... 5
JTAG Interface............................................................................................................................. 5
Block Diagram ................................................................................................................................... 6
Block Diagram Description ................................................................................................................ 7
Envoy-8FE Interfaces .................................................................................................................. 7
Lead Diagram .................................................................................................................................. 11
Lead Descriptions ............................................................................................................................ 12
Absolute Maximum Ratings and Environmental Limitations............................................................ 21
Thermal Characteristics................................................................................................................... 21
Power Requirements ....................................................................................................................... 22
Timing Characteristics ..................................................................................................................... 24
POS-PHY Level 2 ...................................................................................................................... 27
Microprocessor Interface Timing................................................................................................ 32
Input, Output and Input/Output Parameters..................................................................................... 22
Microprocessor Interface ............................................................................................................. 5
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Ethernet Half Duplex........................................................................................................................ 42
Memory Information......................................................................................................................... 46
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Memory Maps and Bit Descriptions ................................................................................................. 47
Package Information........................................................................................................................ 82
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Standards Documentation Sources ................................................................................................. 85
Please note that TranSwitch provides documentation for all of its products. Current editions of many documents
are available from the Products page of the TranSwitch Web site at
www.transwitch.com.
Customers who are using
a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive
relevant updated and supplemental documentation as it is issued. They should also contact the Applications
Engineering Department to ensure that they are provided with the latest available information about the product,
especially before undertaking development of new designs incorporating the product.
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Application Example ........................................................................................................................ 84
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Related Products ............................................................................................................................. 83
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Ordering Information........................................................................................................................ 83
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Ethernet Full Duplex Flow Control ............................................................................................. 44
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POS-PHY Level 2/SPI-3 to SMII Flow Functional Operation..................................................... 38
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SMII to POS-PHY Level 2/SPI-3 Flow Functional Operation..................................................... 34
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Operation ......................................................................................................................................... 34
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OIF SPI-3 ................................................................................................................................... 29
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PRODUCT PREVIEW
TXC-06840-MB
Ed. 1, January 2003
PRODUCT PREVIEW
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-8FE
TXC-06840
LIST OF FIGURES
Figure
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Page
Functional Block Diagram of the Envoy-8FE ............................................................ 6
Envoy-8FE TXC-06840 376-Lead Plastic Ball Grid Array Package Lead Diagram 11
SMII Sync In/Out Timing......................................................................................... 24
SMII Transmit Interface Timing .............................................................................. 24
SMII Receive Interface Timing ............................................................................... 25
Transmit Interface Timing (POS-PHY Level 2)....................................................... 27
Receive Interface Timing (POS-PHY Level 2)........................................................ 28
Receive Interface Timing (OIF SPI-3)..................................................................... 30
MPC860 Single Write Cycle Timing........................................................................ 31
MPC860 Single Read Cycle Timing ....................................................................... 32
Boundary Scan Timing Diagram............................................................................. 33
Envoy-8FE TXC-06840 Package Diagram ............................................................. 82
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Ethernet Over VDSL Application Using Envoy-8FE Device ................................... 84
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Transmit Interface Timing (OIF SPI-3).................................................................... 29
PRODUCT PREVIEW
TXC-06840-MB
Ed. 1, January 2003
PRODUCT PREVIEW
MII Interface Timing ................................................................................................ 26
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-8FE
TXC-06840
FEATURES
10/100 MBIT/S MEDIA ACCESS CONTROLLER (MAC) BLOCK
The main features supported by the MAC block are as follows:
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Compliant to IEEE 802.3, 802.3i, 802.3u, 802.3x
Mixed 10/100 Mbit/s mode
Full Duplex and Half Duplex (CSMA/CD) operation per MAC
Connection to standard 10/100 Mbit/s Fast Ethernet PHY devices via SMII interface
Frame Integrity Verification (FCS and length checks)
Errored Frames can be configured to be filtered
Programmable Inter-Packet Gap (IPG) between Ethernet frames
Programmable frame length
• Minimum frame size = 64 bytes
• Maximum frame size = 1550 bytes
Support for VLAN tagged frames
Programmable High and Low FIFO watermarks for space and frame availability generation
MAC control sublayer provides support for control frames including PAUSE frames
Automatic PAUSE Frame Generation and Termination
7.7 x 1550 byte ingress FIFO per MAC
2.6 x 1550 byte egress FIFO per MAC
Far end switch side loopback for diagnostic capability
Statistics and performance monitoring support for Remote Network Monitoring (RMON)
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The Envoy-8FE provides the following Ethernet Port features:
• 8 independent SMII ports operating at 10/100 Mbit/s mixed mode
• Each SMII port is comprised of:
• Two serial data signals (TX and RX) per port
• Global 125 MHz reference clock signal for all eight ports
• Global synchronization signal for all eight ports
• All signals are synchronous to the clock
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Envoy-8FE provides 8 independent SMII interfaces with an IEEE 802.3 compliant MAC connected to each
interface/port. Data received at the SMII interface is first qualified by a MAC and then passed onto a 7.7 x 1550
Byte FIFO. The MAC is configured to operate in either Full-Duplex or Half-Duplex Mode. Once the MAC has
processed the frame, it updates statistics which are stored in the Envoy-8FE status registers. These registers
are used to provide performance monitoring. PAUSE frames received are used to backpressure the POS-PHY
Level 2/OIF SPI-3 interface for that specific port. When the Ingress FIFO reaches a watermark, PAUSE frames
are generated and transmitted over the SMII interface to the MII PHY (if enabled). Once the Egress FIFO has a
complete frame to send, the SMII transmit interface attempts to transmit the frame over its SMII interface. In
Half-Duplex mode, CSMA/CD is used to determine selection. In Full-Duplex mode, CSMA/CD is not used per
IEEE 802.3.
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SERIAL MEDIA INDEPENDENT INTERFACE (SMII)
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PRODUCT PREVIEW
TXC-06840-MB
Ed. 1, January 2003
PRODUCT PREVIEW
W
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Envoy-8FE
TXC-06840
A single Ethernet Management interface is provided on the Envoy-8FE to connect to an external Ethernet PHY
in order to configure and control its operation. This interface is comprised of an output Management Data clock
signal and a bi-directional Management Data signal that allows serial data to be clocked in and out of the exter-
nal PHY device. All data transfers are synchronous to the clock signal and provide support for up to 31 PHYs
(PHY Address = 0 is reserved).
POS-PHY LEVEL 2/SPI-3 INTERFACE
The Envoy-8FE POS-PHY Level 2/SPI-3 interface is a slave (PHY) interface operating at rates up to 50/100
MHz. The flow control is frame-based for POS-PHY Level 2, and both byte and frame based for SPI-3. In the
POS-PHY Level 2/SPI-3 Receive direction (Envoy-8FE Ingress i.e., SMII to POS-PHY Level 2/SPI-3), when a
port has a complete frame to send or a pre-configured number of bytes, the port indicates availability of data
for transfer. A port is then selected for transferring data based on selection by the Link Layer POS-PHY
Level 2/SPI-3 device. In the Transmit direction (Envoy-8FE Egress i.e., POS-PHY Level 2/SPI-3 to SMII), FIFO
space availability is indicated to the Link Layer POS-PHY Level 2/SPI-3 device when a specific watermark is
reached.
MICROPROCESSOR INTERFACE
JTAG INTERFACE
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This interface provides a five signal Boundary Scan capability that conforms to the IEEE 1149.1 standard. This
standard provides external boundary scan functions to read and write the external I/O pins from the Test
Access Port (TAP) for board and component test. In addition to the TAP a lead is provided to place the output
,
buffers in a high impedance state for systems that do not support the IEEE 1149.1 standard.
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A Motorola Microprocessor compliant interface (32-bit wide data bus) is used to configure the part and retrieve
status from Envoy-8FE. It is compatible with the PowerQUICC family of microprocessors from Motorola
including the MPC860, operating at 33/50 MHz.
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PRODUCT PREVIEW
TXC-06840-MB
Ed. 1, January 2003
PRODUCT PREVIEW
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