DDR SDRAM 256Mb E-die (x8)
DDR SDRAM
256Mb E-die DDR400 SDRAM Specification
sTSOP(II)
(300mill x 551mil)
Revision 1.0
Rev. 1.0 August. 2003
DDR SDRAM 256Mb E-die (x8)
256Mb E-die Revision History
Revision 1.0 (August, 2003)
- First release
DDR SDRAM
Rev. 1.0 August. 2003
DDR SDRAM 256Mb E-die (x8)
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP(II)-300 package
DDR SDRAM
Ordering Information
Part No.
K4H560838E-NCCC
K4H560838E-NCC4
32M x 8
Org.
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Interface
SSTL2
Package
54pin sTSOP(II)-300
Operating Frequencies
- CC(DDR400@CL=3)
Speed @CL3
CL-tRCD-tRP
*CL : CAS Latency
200MHz
3-3-3
- C4(DDR400@CL=3)
200MHz
3-4-4
Rev. 1.0 August. 2003
DDR SDRAM 256Mb E-die (x8)
Pin Description
DDR SDRAM
54pin sTSOP(II)-300
32Mb x 8
VDD
DQ0
VDDQ
DQ1
VSSQ
DQ2
VDDQ
DQ3
VSSQ
NC
VDDQ
NC
NC
VDD
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
VSSQ
DQS
VREF
VSS
DM
CK
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
54 PinsTSOP(II)
300mil x 551mil
(7.62mm x 14.00mm)
(0.5 mm Pin Pitch)
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Organization
32Mx8
Row Address
A0~A12
Column Address
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.0 August. 2003
DDR SDRAM 256Mb E-die (x8)
Package Physical Dimension
54pin sTSOP(II)-300
DDR SDRAM
Units : Millimeters
(0.50)
(14
°
)
(0.50)
(8.22)
(0.80)
0.125
+0.075
-0.035
(2-R 0.15)
#54
#28
(0.80)
(2-R 0.30)
(∅ 2.00 Dp0~0.05 BTM)
9.22±0.20
(1.00)
(1.00)
#1
#27
0.665±0.05
0.210±0.05
7.6
0.1
5)
(1.10)
(R
0.2
5
0.10 MAX
)
0.
30
)
(14
°
)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
0.05 MIN
(0.50)
0.50TYP
0.50±0.05
[
0.07 MAX ]
+0.075
0.20
-0.035
(2
-R
0×~8×
Rev. 1.0 August. 2003
(R
0.
25
)
(14
°
)
(2-
R
(14
°
)
1.00±0.05
1.20MAX
14.40MAX
(14.20)
14.00±0.10
0.25TYP
0.40~0.60
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