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K4F640412D-TI60T

产品描述Fast Page DRAM, 16MX4, 60ns, CMOS, PDSO32,
产品类别存储    存储   
文件大小172KB,共20页
制造商SAMSUNG(三星)
官网地址http://www.samsung.com/Products/Semiconductor/
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K4F640412D-TI60T概述

Fast Page DRAM, 16MX4, 60ns, CMOS, PDSO32,

K4F640412D-TI60T规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称SAMSUNG(三星)
包装说明TSOP, TSOP32,.46
Reach Compliance Codecompliant
最长访问时间60 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-G32
内存密度67108864 bit
内存集成电路类型FAST PAGE DRAM
内存宽度4
端子数量32
字数16777216 words
字数代码16000000
最高工作温度85 °C
最低工作温度-40 °C
组织16MX4
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSOP
封装等效代码TSOP32,.46
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE
电源3.3 V
认证状态Not Qualified
刷新周期4096
自我刷新NO
最大待机电流0.0005 A
最大压摆率0.1 mA
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL

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Industrial Temperature
K4F660412D,K4F640412D
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low pow er)
are optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung
′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
CMOS DRAM
FEATURES
• Part Identification
- K4F660412D-JI/P(3.3V, 8K Ref., SOJ)
- K4F640412D-JI/P(3.3V, 4K Ref., SOJ)
- K4F660412D-TI/P(3.3V, 8K Ref., TSOP)
- K4F640412D-TI/P(3.3V, 4K Ref., TSOP)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
Active Power Dissipation
Unit : mW
Speed
-45
-50
-60
Refresh Cycles
Part
NO.
K4F660412D*
K4F640412D
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
Control
Clocks
Vcc
Vss
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V
±0.3V
power supply
Industrial Temperature operating
( -40~85
°C
)
4K
432
396
360
8K
324
288
252
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
Refresh Control
Refresh Counter
Memory Array
16,777,216 x 4
Cells
Sense Am ps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Performance Range
Speed
-45
-50
-60
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
80ns
90ns
110ns
t
PC
31ns
35ns
40ns
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.

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