S E M I C O N D U C T O R
CD74FCT16501T,
CD74FCT162501T
Fast CMOS 18-Bit Registered Transceiver
Ordering Information
TEMP.
RANGE
(
o
C)
PKG.
NO.
December 1996
Features
• Advanced 0.6 micron CMOS Technology
• These Devices are High-speed, Low Power Devices
with High Current Drive
• V
CC
= 5V
±10%
• Hysteresis on All Inputs
• CD74FCT16501T
- High Output Drive: I
OH
= -32mA; I
OL
= 64mA
- Power Off Disable Outputs Permit "Live Insertion"
- Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
o
C
• CD74FCT162501T
- Balanced Output Drivers:
±24mA
- Reduced System Switching Noise
- Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25
o
C
PART NUMBER
CD74FCT16501ATMT
CD74FCT16501ATSM
CD74FCT16501CTMT
CD74FCT16501CTSM
CD74FCT16501DTMT
CD74FCT16501DTSM
CD74FCT16501ETMT
CD74FCT16501ETSM
CD74FCT162501ATMT
CD74FCT162501ATSM
CD74FCT162501CTMT
CD74FCT162501CTSM
CD74FCT162501DTMT
CD74FCT162501DTSM
CD74FCT162501ETMT
CD74FCT162501ETSM
PACKAGE
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
Description
These devices are 18-bit are registered bus transceivers
designed with D-type latches and flip-flops to allow data flow
in transparent, latched, and clocked modes. The Output
Enable (OEAB and OEBA, Latch Enable (LEAB and LEBA)
and Clock (CLKAB and CLKBA) inputs control the data flow
in each direction. When LEAB is HIGH, the device operates
in transparent mode for A-to-B data flow. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH or
LOW logic level. The A bus data is stored in the latch/flip-
flop on the HIGH-to-LOW transition of CLKAB, if LEAB is
LOW. OEAB performs the output enable function on the B
port. Data flow from B port to A port is similar using OEBA,
LEBA and CLKBA. These high-speed, low power devices
offer a flow-through organization for ease of board layout.
The CD74FCT16501T output buffers are designed with a
Power-Off disable allowing "live insertion" of boards when
used as backplane drivers.
The CD74FCT162501T has 24 mA balanced output drivers.
It is designed with current limiting resistors at its outputs to
control the output edge rate resulting in lower ground bounce
and undershoot. This eliminates the need for external termi-
nating resistors for most interface applications.
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
-40 to 85 56 Ld TSSOP M56.240-P
-40 to 85 56 Ld SSOP
M56.300-P
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
File Number
4184.1
1
CD74FCT16501T, CD74FCT162501T
Pinout
CD74FCT16501T, CD74FCT162501T
(SSOP, TSSOP)
TOP VIEW
OEAB
LEAB
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
0
GND
B
1
B
2
V
CC
B
3
B
4
B
5
GND
B
6
B
7
B
8
B
9
B
10
B
11
GND
B
12
B
13
B
14
V
CC
B
15
B
16
GND
B
17
CLKBA
GND
2
CD74FCT16501T, CD74FCT162501T
Functional Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
0
D
C
D
B
0
C
D
C
D
TO 17 OTHER CHANNELS
TRUTH TABLE
(NOTES 1 AND 4)
INPUTS
OEAB
L
H
H
H
H
H
H
NOTES:
19. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
20. Output level before the indicated steady-state input conditions were established.
21. Output level before the indicated steady-state input conditions wer established, provided that
CLKAB was LOW before LEAB went LOW.
22. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
↑
= LOW-to-HIGH Transition
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
A
X
X
L
H
L
H
X
X
OUTPUTS
B
X
Z
L
H
L
H
B (Note 2)
B (Note 3)
3
CD74FCT16501T, CD74FCT162501T
Pin Descriptions
PIN NAME
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
A
X
B
X
GND
V
CC
DESCRIPTION
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A
Three-State Outputs (Note 5)
B-to-A Data Inputs or A-to-B
Three-State Outputs (Note 5)
Ground
Power
4
CD74FCT16501T, CD74FCT162501T
Absolute Maximum Ratings
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA
Thermal Information
Thermal Resistance (Typical, Note 5)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage to Ground Potential
Inputs and V
CC
Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
23.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS
SYMBOL
(NOTE 6)
TEST CONDITIONS
MIN
(NOTE 7)
TYP
MAX
UNITS
DC ELECTRICAL SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±10%
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
Input LOW Current
High Impedance
Output Current
(Three-State)
(Note 9)
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
V
IH
V
IL
I
IH
I
IH
I
IL
I
IL
I
OZH
I
OZL
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input,V
CC
= Max
Standard I/O, V
CC
= Max
Standard Input, V
CC
= Min
Standard I/O, V
CC
= Min
V
CC
= Max
V
CC
= Max
V
IN
= V
CC
V
IN
= V
CC
V
IN
= GND
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1
1
-1
-1
1
-1
V
V
µA
µA
µA
µA
µA
µA
V
IK
I
OS
I
O
V
H
V
CC
= Min, I
IN
= -18mA
V
CC
= Max (Note 8), V
OUT
= GND
V
CC
= Max (Note 8), V
OUT
= GND
-
-80
-50
-
-0.7
-140
-
100
-1.2
-200
-180
-
V
mA
mA
mV
CD74FCT16501T OUTPUT DRIVE SPECIFICATIONS
Over the Operating Range
Output HIGH Voltage
V
OH
V
CC
= Min, V
IN
= V
IH
or V
IL
I
OH
= -3.0mA
I
OH
= -15.0mA
I
OH
= -32.0mA
Output LOW Voltage
Power Down Disable
V
OL
I
OFF
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
OUT
≤
4.5V
I
OL
= 64mA
2.5
2.4
2.0
-
-
3.5
3.5
3.0
0.2
-
-
-
-
0.55
±100
V
V
V
V
µA
CD74FCT162501T OUTPUT DRIVE SPECIFICATIONS
Over the Operating Range
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
V
OH
V
OL
I
ODL
I
ODH
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= Min, V
IN
= V
IH
or V
IL
I
OH
= -24.0mA
I
OL
= 24mA
2.4
-
60
-60
3.3
0.3
115
-115
-
0.55
150
-150
V
V
mA
mA
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V (Note 10)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V (Note 10)
CAPACITANCE
T
A
= 25
o
C, f = 1MHz
Input Capacitance
(Note 10)
Output Capacitance
(Note 10)
C
IN
C
OUT
V
IN
= 0V
V
OUT
= 0V
-
-
4.5
5.5
6
8
pF
pF
5
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