IDT54/74FCT16500/AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS 18-BIT
REGISTERED
TRANSCEIVER
FEATURES:
−
−
−
−
−
−
−
−
−
−
−
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤1µ
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP
and 25 mil pitch CERPACK packages
Extended commercial range of -40°C to +85°C
V
CC
= 5V ±10%
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V, T
A
=
25°C
IDT54/74FCT16500/AT/CT/ET
DESCRIPTION:
The FCT16500AT/CT/ET 18-bit registered transceivers are built using
advanced dual metal CMOS technology. These high-speed, low-power
18-bit registered bus transceivers combine D-type latches and D-type flip-
flops to allow data flow in transparent, latched and clocked modes. Data flow
in each direction is controlled by output-enable (OEAB and
OEBA),
latch
enable (LEAB and LEBA) and clock (CLKAB and
CLKBA)
inputs. For A-
to-B data flow, the device operates in transparent mode when LEAB is high.
When LEAB is low, the A data is latched if
CLKAB
is held at a high or low
logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the
high-to-low transition of
CLKAB.
OEAB performs the output enable function
on the B port. Data flow from B port to A port is similar but uses
OEBA,
LEBA
and
CLKBA.
Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
The FCT16500AT/CT/ET are ideally suited for driving high-capaci-
tance loads and low-impedance backplanes. The output buffers are
designed with power off disable capability to allow "live insertion" of boards
when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
1
30
28
27
55
2
C
A
1
3
C
D
54
D
B
1
C
D
C
D
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
c
1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-5433/-
IDT54/74FCT16500/AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S O 5 6 -1
S O 5 6 -2
S O 5 6 -3
E 5 6 -1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1,4)
Inputs
Outputs
CLKAB
X
X
X
↓
↓
H
L
Ax
X
L
H
L
H
X
X
Bx
Z
L
H
L
H
B
(2)
B
(3)
OEAB
LEAB
X
H
H
L
L
L
L
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
L
H
H
H
H
H
H
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input (Active LOW)
B-to-A Clock Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that
CLKAB
was LOW before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↓
= HIGH-to-LOW Transition
2
IDT54/74FCT16500/AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%; Military: T
A
= -55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
5v16-link
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL.
I
OH
= –15mA COM’L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM’L.
(4)
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
I
OL
= 48mA MIL.
I
OL
= 64mA COM’L
—
—
±1
µA
—
0.2
0.55
V
2
3
—
V
Min.
–50
2.5
2.4
Typ.
(2)
—
3.5
3.5
Max.
–180
—
—
Unit
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at T
A
= -55°C.
3
IDT54/74FCT16500/AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
OEAB =
OEBA
= V
CC
or GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKAB)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKAB)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
Eighteen Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
—
3.8
6.5
(5)
V
IN
= 3.4V
V
IN
= GND
—
8.5
20.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT54/74FCT16500/AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16500AT
Com'l.
Mil.
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
Parameter
CLKAB
or
CLKBA
frequency
(4)
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA
to Ax,
CLKAB
to Bx
Output Enable Time
OEBA
to Ax, OEAB to Bx
Output Disable Time
OEBA
to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to
CLKAB,
Bx to
CLKBA
Hold Time, HIGH or LOW
Ax to
CLKAB,
Bx to
CLKBA
Set-up Time
Clock
HIGH or LOW
HIGH
Ax to LEAB,
Clock
Bx to LEBA
LOW
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width HIGH
(4)
C
L
= 50pF
R
L
= 500Ω
—
1.5
1.5
1.5
1.5
1.5
3
0
3
1.5
1.5
3
3
—
150
5.1
5.6
5.6
6
5.6
—
—
—
—
—
—
—
0.5
—
1.5
1.5
1.5
1.5
1.5
3
0
3
1.5
1.5
3
3
—
150
5.6
6
6
6.4
6
—
—
—
—
—
—
—
0.5
FCT16500CT
Com'l.
Mil.
—
1.5
1.5
1.5
1.5
1.5
3
0
3
1.5
1.5
3
3
—
150
4.6
5.3
5.3
5.6
5.2
—
—
—
—
—
—
—
0.5
—
1.5
1.5
1.5
1.5
1.5
3
0
3
1.5
1.5
3
3
—
150
4.6
5.6
5.4
6
5.6
—
—
—
—
—
—
—
0.5
FCT16500ET
Com'l.
Mil.
—
—
—
—
—
—
2.4
0
2
1.5
0.5
3
3
—
150
3.8
4.2
4.2
4.8
4
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
H
t
W
t
W
CLKAB
or
CLKBA
Pulse Width
HIGH or LOW
(4)
t
SK
(o) Output Skew
(3)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5
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