MGA-13216
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-13216 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ propri-
etary 0.25
Pm
GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
It is designed for optimum use between 1.5 GHz to 2.5
GHz. For optimum performance at lower frequency from
400 MHz to 1.5 GHz, the MGA-13116 is recommended.
Both MGA-13216 & MGA-13116 share the same package
and pinout configuration.
Features
x
Optimum frequency of operation 1.5 GHz – 2.5 GHz
x
Very low noise figure
x
High gain
x
High linearity performance
x
Excellent isolation
x
GaAs E-pHEMT Technology
[1]
x
Low cost small package size: 4.0 x 4.0 x 0.85 mm
3
Specifications
1.95 GHz; Q1: 5 V, 53 mA (typ) Q2: 5 V, 122 mA (typ)
x
x
x
x
x
0.61 dB Noise Figure
35.8 dB Gain
46 dB RFoutQ1 to RFinQ2 Isolation
40.5 dBm Output IP3
23.6 dBm Output Power at 1dB gain compression
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm
3
16-lead QFN
13
14
15
16
AVAGO
13216
YYWW
XXXX
12
11
10
9
8
7
6
5
GND
1
2
3
4
Pin
2
Pin
3
Pin 10
Pin 11
Pin 13
Pin 16
Vbias
RFinQ1
RFoutQ2
RFoutQ2
RFinQ2
RFoutQ1
Applications
x
Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x
Other very low noise applications.
All other pins
NC
–
Not Connected
TOP VIEW
BOTTOM VIEW
Simplified Schematic
Vdd1
C9
R3
C8
C10
R4
R2
C7
L3
C6
16
1
15
Note:
Package marking provides orientation and identification
“13216” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
Vdd2
C5
C4
R1
14 13
12
11
Q2
10
9
8
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 650 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
C3
L1
RFIN C1
2 Q1bias
3
4
5
6
7
Q1
L2
C2
RFOUT
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
MGA-13216 Absolute Maximum Rating
[1]
TA = 25° C
Symbol
Vdd1
Vdd2
Idd1
P
d
P
in,max
T
j,max
T
stg
Thermal Resistance
[3]
Units
V
V
mA
W
dBm
°C
°C
Parameter
Device Voltage
Device Voltage
Q1 Drain Current
Power Dissipation
(2)
CW RF Input Power
Junction Temperature
Storage Temperature
Absolute Maximum
5.5
5.5
90
1.11
20
150
-65 to 150
(V
dd1
=5.0V, I
dd1
=53mA, V
dd2
=5.0V,
I
dd2
=122mA)
T
jc
= 40.3° C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Board temperature (T
c
) is 25° C. For T
c
>100° C,
derate the device power at 24.8 mW per °C
rise in board temperature adjacent to pack-
age bottom.
3. Thermal resistance measured using Infrared
Measurement Technique.
Electrical Specifications
[1]
RF performance at Vdd1 = 5 V, Vdd2 = 5 V, 1.95 GHz, T
A
= 25° C, measured on the demo board for 1.95 GHz matching.
Symbol
Idd1
Idd2
NF
Gain
OIP3
[2]
OP1dB
IRL
ORL
|S12|
|ISOL
1-2
|
Parameter and Test Condition
Current at Q1
Current at Q2
Noise Figure
Gain
Output Third Order Intercept Point
Output Power at 1 dB Gain Compression
Input Return Loss, 50
:
source
Output Return Loss, 50
:
load
Reverse Isolation
Isolation between Q1’s Output pin & Q2’s Input pin
Units
mA
mA
dB
dB
dBm
dBm
dB
dB
dB
dB
Min.
39
101
–
34.3
37
22.3
–
–
–
–
Typ.
53
122
0.61
35.8
40.5
23.6
-18
-10.7
55
46
Max.
67
143
0.9
37.3
–
–
–
–
–
–
Notes:
1. Measurements obtained using demo board described in Figure 7 with component list in Table 1. Input and Output trace loss is not de-embedded
from the measurement.
2. OIP3 test condition: f
tone1
= 1.95 GHz, f
tone2
= 1.951 GHz with input power of -27 dBm per tone.
3. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product consistency Distribution Charts
[1,2]
LSL
USL
LSL
USL
40
50
60
100
110
120
130
140
Figure 1. Idd1 @ 1. 95 GHz, Vdd1 = 5 V, LSL = 39 mA, Nominal = 53 mA,
USL = 67 mA
Figure 2. Idd2 @ 1.95 GHz, Vdd2 = 5 V, LSL = 101 mA, Nominal = 122 mA,
USL = 143 mA
USL
LSL
USL
0.4
0.5
0.6
0.7
0.8
0.9
35
36
37
Figure 3. Noise Figure @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V,
Nominal = 0.61 dB, USL = 0.9 dB
Figure 4. Gain @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 34.3 dB,
Nominal = 35.8 dB, USL = 37.3 dB
LSL
LSL
37
38
39
40
41
42
43
22.5
23
23.5
24
24.5
Figure 5. OIP3 @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 37 dBm,
Nominal = 40.5 dBm
Figure 6. OP1dB @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 22.3 dBm,
Nominal = 23.6 dBm
Notes:
1. Data sample size is 9193 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere
between the upper and lower limits.
2. Measurements are made on production test board which represents a trade-off between optimal Gain, NF, OIP3 and OP1dB. Circuit losses have
been de-embedded from actual measurements.
3
Demo Board Layout
VDD1
VDD2
GND
VBias
GND
Demo Board Schematic
Vdd1
R5
C10 C12
R2
Vdd2
GND
R4b
R4a
C9b
C9a
R3
C8
C11
C1 L1
L4
C9
C10
R4
R2
C7
R3
C5
C4
R1
14 13
12
11
Q2
10
9
5
6
7
8
L2
C2
RFOUT
C3
IN
C7 L3
C6 R1
C5b
C5a
C4
C3
OUT
L2
C2
L5
C13
C8
L3
C6
16 15
1
L1
2 Q1bias
3
Q1
JAN 2011
AVAGO
Technologies
RFIN
C1
4
MANGROVE
Figure 7. Demo Board layout diagram.
Figure 8. Demo Board schematic diagram.
– Recommended PCB material is 10 mils Rogers R04350.
– Suggested component values may vary according to layout and PCB material.
Table 1. Component list for 1.95GHz matching
Part
C1
C2
C3
C4
C5a
C6
C7, C8
C9a, C10
C9b
L1
L2
L3
R1, R2
R3
R4b
Size
0402
0402
0402
0402
0603
0402
0402
0402
N/A
0402
0402
0402
0402
0402
0402
Value
10pF (Murata)
100pF (Murata)
3.3pF (Murata)
0.1uF (Murata)
2.2uF (Murata)
1000pF (Murata)
10pF (Murata)
4.7uF (Murata)
Not used
5.6nH (Toko)
4.7nH (Toko)
100nH (Toko)
0 ohm (Koa)
49.9 ohm (Koa)
4.7K ohm (Rohm)
Detail Part Number
GRM1555C1H100JZ01E
GRM1555C1H101JD01E
MCH155A3R3JK
GRM155R61A104KA01D
GRM188R61A225KE34D
GRM155R71H102KA01E
GRM1555C1H100JZ01E
GRM155R60E475ME760
Not used
LL1005-FHL5N6S
LL1005-FH4N7S
LL1005-FHLR10J
RK73Z1ELTP
RK73H1ELTP49R9F
MCR01J472
Notes
DC Blocking Capacitor
DC Blocking Capacitor
Bypass Capacitor
Bypass Capacitor
Bypass Capacitor
DC Blocking Capacitor
Bypass Capacitors
Bypass Capacitors
Bypass Capacitors
Input match for NF
Output match for Q2
Output match for Q1
Bridging Resistors
Stabilizing Resistor for Q1
Biasing Resistor for Q1
4
MGA-13216 Typical Performance in Demoboard for 1.95 GHz
T
A
= 25° C, V
dd1
= 5.0 V, V
dd2
= 5.0 V, I
dd1
= 53 mA, I
dd2
= 122 mA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1300
1500
1700
1900
2100
Frequency (MHz)
2300
85° C
25° C
-40°
C
2500
2700
32.0
30.0
1300
Gain (dB)
NF
(dB)
40.0
38.0
36.0
34.0
85° C
25° C
-40°
C
1500
1700
1900
2100 2300
Frequency (MHz)
2500
2700
Figure 9. NF vs Frequency and Temperature
Figure 10. Gain vs Frequency and Temperature
50.0
45.0
40.0
35.0
30.0
25.0
1300
85° C
25° C
-40°
C
1500
1700
1900
2100 2300
Frequency (MHz)
2500
2700
OP1dB
(dBm)
26.0
OIP3
(dBm)
24.0
22.0
85° C
25° C
-40°
C
20.0
1300
1500
1700
1900
2100 2300
Frequency (MHz)
2500
2700
Figure 11. OIP3 vs Frequency and Temperature
Figure 12. OP1dB vs Frequency and Temperature
50
IRL,
ORL,
Gain,
Rev
Isol (dB)
30
10
-10
-30
-50
-70
0
S11
S22
S21
S12
1
2
3
Frequency (GHz)
4
5
10
9
8
7
6
5
4
3
2
1
0
85° C
25° C
-40°
C
K - factor
0
2
4
6
8
10 12
Frequency (GHz)
14
16
18
20
Figure 13. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation
vs Frequency
Figure 14. K-factor vs Frequency and Temperature
5
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