HY5DU56422C(L)T
HY5DU56822C(L)T
HY5DU561622C(L)T
DESCRIPTION
The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density and high band-
width.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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V
DD
/V
DDQ
= 2.5 +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
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All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
CAS latency 1.5, 2 ,2.5 & 3 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
tRAS Lock-out function supported
Auto refresh and Self refresh supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
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ORDERING INFORMATION
Part No.
HY5DU56422CT-*
HY5DU56822CT-*
HY5DU561622CT-*
OPERATING FREQUENCY
Package
400mil
66pin
TSOP-II
Configuration
64Mx4
32Mx8
16Mx16
Grade
-J
-M
-K
-H
-L
CL2
133MHz
133MHz
133MHz
100MHz
100MHz
CL2.5
166MHz
133MHz
133MHz
133MHz
125MHz
Remark
(CL-tRCD-tRP)
DDR333 (2.5-3-3)
DDR266 (2-2-2)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
* Note : * indicates speed Grade.
* CL1.5 @ DDR200 supported
* CL3 supported
Rev. 0.4 / Jan. 2004
2
HY5DU56422C(L)T
HY5DU56822C(L)T
HY5DU561622C(L)T
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit,
and for output disable. CKE must be maintained high throughout READ and WRITE
accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an
SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All
com-mands are masked when CS is registered high. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or
PRE-CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 is sampled during a
precharge command to determine whether the PRECHARGE applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA0, BA1. The address inputs also provide the op code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register is loaded during
the MODE REGISTER SET command (MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM
corre-sponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to
the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin : Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CK, /CK
Input
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A12
Input
/RAS, /CAS, /WE
Input
DM
(LDM, UDM)
Input
DQS
(LDQS, UDQS)
DQ
VDD/ VSS
VDDQ/ VSSQ
VREF
NC
I/O
I/O
Supply
Supply
Supply
NC
Rev. 0.4 / Jan. 2004
4
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