IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
FEATURES:
DESCRIPTION:
IDT54/74FCT823A/B/C
• Equivalent to AMD's Am29823 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
• IDT54/74FCT823A equivalent to FAST™ speed
• IDT54FCT823B 25% faster than FAST
• IDT74FCT823C 40% faster than FAST
• Buffered common Clock Enable (EN) and Asynchronous Clear
Input (CLR)
• I
OL
= 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD's bilopar
Am29800 series (5µA max.)
µ
• MIlitary product compliant to MIL-STD-883, Class B
• Available in the following packages:
– Commercial: SOIC
– Military: CERDIP, LCC
The FCT823 series is built using an advanced dual metal CMOS
technology. The FCT823 bus interface registers are designed to eliminate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear
(CLR) – ideal for parity bus interfacing in high-performance microprogram-
med systems.
The FCT823 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
D
0
14
D
N
EN
CLR
11
D
CL
Q
Q
D
CL
Q
Q
CP
CP
CP
13
OE
1
Y
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y
N
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-5426/3
© 2002 Integrated Device Technology, Inc.
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE
D
1
NC
D
0
Y
0
27
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
2
3
4
5
6
7
8
9
10
11
12
23
22
21
20
19
18
17
16
15
14
13
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
D
2
D
3
D
4
NC
D
5
D
6
D
7
5
6
7
8
9
10
4
3
2
1
28
26
25
24
23
22
21
20
19
Y
1
INDEX
V
CC
OE
1
24
V
CC
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
11
12
13
14
15
16
17
18
GND
CLR
NC
D
8
EN
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature under BIAS
Storage Temperature
Power Dissipation
DC Output Current
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
–0.5 to V
CC
–0.5 to V
CC
V
Commercial
–0.5 to +7
Military
–0.5 to +7
Unit
V
LOGIC SYMBOL
9
D
D
Q
CP
CP
EN
CLR
OE
EN
CLR
9
Y
PIN DESCRIPTION
Pin Name
Dx
CLR
I/O
I
I
Description
D flip-flop data inputs
For both inverting and non-inverting registers, when
the clear input is LOW and
OE
is LOW, the Q
x
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Register 3-state outputs
Clock Enable. When the clock enable is LOW, data
on the D
I
input is transferred to the Q
I
output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change state,
regardless of the data or clock input transitions.
Output Control. When the
OE
input is HIGH, the Yx
outputs are in the high impedance state. When the
OE
input is LOW, the TRUE register data is present at the
Yx outputs.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
CP
Yx
EN
I
O
I
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
OE
I
2
CP
Y
8
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
(1)
Inputs
OE
H
H
H
L
H
L
H
H
L
L
CLR
H
H
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
Dx
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Internal/
Outputs
Qx
Yx
L
Z
H
Z
L
Z
L
L
NC
Z
NC NC
L
Z
H
Z
L
L
H
H
Function
High Z
Clear
Hold
Load
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V ±5%, Military: T
A
= -55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
OH
Off State (High Impedance)
Output Current
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Max.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
V
CC
= Max.
Input LOW Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Min.
2
—
—
—
—
—
—
—
—
—
—
–75
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC
(4)
0.5
0.5
µA
µA
Unit
V
V
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
V
CC
= Min
I
OH
= –300µA
I
OH
= –15mA MIL
V
IN
= V
IH
or V
IL
I
OH
= –24mA COM'L
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
V
CC
= Min
I
OL
= 300µA
I
OL
= 32mA MIL
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L
V
mA
V
V
OL
Output LOW Voltage
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
3
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
at fi = 2.5MHz
Eight Bits Toggling
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4
mA
—
2.2
6
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
4
7.8
(5)
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + fiNi)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT823A
Com'l.
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CP to Yx (OE = LOW)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(3)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(3)
R
L
= 500Ω
C
L
= 5pF
(3)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
—
—
—
—
—
—
4
2
2
—
6
7
6
Max.
10
20
12
23
7
8
—
—
—
14
—
—
—
Min.
(2)
—
—
—
—
—
—
4
2
2
—
7
7
7
Mil.
Max.
11.5
20
13
25
8
9
—
—
—
15
—
—
—
54FCT823B
Mil.
Min.
(2)
Max.
—
8.5
—
—
—
—
—
3
1.5
0
—
6
6
6
16
9
16
7
8
—
—
—
9.5
—
—
—
74FCT823C
Com'l.
Min.
(2)
Max.
—
6
—
—
—
—
—
3
1.5
0
—
6
6
6
12.5
7
12.5
6.2
6.5
—
—
—
8
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
t
PZH
t
PZL
Output Enable Time,
OE
to Yx
t
PHZ
t
PLZ
Output Disable Time,
OE
to Yx
t
SU
t
H
t
H
t
PHL
t
REM
t
W
t
W
Set-up Time HIGH or LOW, Dx to CP
Set-up Time HIGH or LOW,
EN
to CP
Hold Time HIGH or LOW, Dx to CP
Hold Time HIGH or LOW,
EN
to CP
Propagation Delay,
CLR
to Yx
Recovery Time,
CLR
to CP
CP Pulse Width HIGH or LOW
CLR
Pulse Width HIGH or LOW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
