155 Mb/s Single Mode Fiber
Transceiver with Integrated
Clock and Data Recovery for
ATM, SONET OC-3/SDH STM-1
Technical Data
Features
• 1300 nm Single Mode
Transceiver for Links up to
15 Km
• Compliant with ATM Forum
155.52 Mb/s Physical Layer
Specification
AF-PHY-0046.000
• Compliant with Specifica-
tions Proposed to ANSI
T1E1.2 Committee for
Inclusion in T1.646-1995
Broadband ISDN and
T1E1.2/96-002 SONET
Network to Customer
Installation Interface
Standards
• Compliant with ANSI
T1.105.06 SONET Physical
Layer Specifications
Standard
• Multisourced 2 x 9 Pin-out
Package Style
• Integral Duplex SC
Connector Receptacle
Compliant with TIA/EIA and
IEC Standards
• Single +5 V Power Supply
Operation and PECL Logic
Interfaces
• Incorporates Hewlett-
Packard’s Eyesafe Laser
Subassembly
• Integral Digital PLL
Provides Regenerated
Differential Clock Output
• Integral Decision Circuit
Provides Retimed
Differential Data Output
• Laser Bias Monitor, Refer-
ence Clock, Transmitter
Disable and Laser Power
Monitor Functions
• Two Temperature Ranges:
0
°
C to +70
°
C - HFCT-5202B/D
–40
°
C to +85
°
C – HFCT-
5202A/C
• Wave Solder and Aqueous
Wash Process Compatible
• Manufactured in an ISO
9001 Certified Facility
HFCT-5202
Description
General
The HFCT-5202 is a 1300 nm
laser-based duplex SC receptacle
2 x 9 transceiver with integral
clock and data recovery circuits.
It provides a cost-effective
solution to medium haul 155 Mb/s
data link requirements.
This compact transceiver requires
a single +5 V source and contains
the following data, clock and
monitoring features as depicted
in Figure 1: differential data
input, differential retimed data
output, recovered clock output,
signal detect, laser bias monitor,
transmitter disable, and an option
Applications
• ATM 155 Mb/s Links
• SONET OC-3/SDH STM-1
Interconnections
2
ELECTRICAL SUBASSEMBLY
RETIMED DATA 2
RECOVERED CLOCK 2
REFERENCE CLOCK
LOCK-TO-REFERENCE
SIGNAL DETECT
DATA
2
LASER
DRIVER
IC
CLOCK & DATA
RECOVERY
AND POST
AMPLIFIER IC
PRE-
AMPLIFIER
IC
OPTICAL
SUB-
ASSEMBLIES
PIN PHOTODIODE
DUPLEX SC
RECEPTACLE
preamplifier IC in an OSA. This
OSA is connected to a custom,
silicon bipolar circuit providing
post-amplification and quantiza-
tion, CDR function, and optical
signal detection.
CDR Function
In normal operation, the CDR
data loop is able to acquire and
maintain bit lock without the use
of the optional, external refer-
ence clock. This loop consists of
a patented phase/frequency
detector with false-lock protec-
tion. The recovered clock is used
to retime the quantizer data
output, which completes the full
CDR function.
The relative timing relationship
between the output retimed data
and the recovered clock signals is
shown graphically in Figure 2.
LASER BIAS MONITOR
LASER
TOP VIEW
POWER
MONITOR
TRANSMIT
DISABLE
Figure 1. Block Diagram.
to generate a local timing signal
from an external, low-frequency
reference clock. The external
timing signal acts as the
reference clock when incoming
optical signals become
undetectable.
Transmitter Section
The transmitter section of the
HFCT-5202 is similar to other
Hewlett-Packard 1300 nm single
mode transceivers in use at the
155 Mb/s data rate. It consists of
a 1300 nm InGaAsP laser in an
eye-safe optical subassembly
(OSA) which mates to the fiber
cable. The laser OSA is driven by
a custom, silicon bipolar IC
which converts differential input
PECL logic signal into an analog
laser drive current.
Receiver Section
The receiver section of the
transceiver provides a full set of
features including an integral
clock and data recovery (CDR)
circuit together with an optional,
selectable receiver local clock
source.
The receiver utilizes an InGaAs
PIN photodiode mounted
together with a transimpedance
BAUD INTERVAL
V
OH
RD
V
OL
V
OH
RD
V
OL
V
OH
CLK
V
OL
V
OH
CLK
V
OL
CLOCK PERIOD
Figure 2. Relative Timing Relationship between Output Retimed Data and
Recovered Clock Signals.
3
For input optical power greater
than the specified receiver
sensitivity of -28 dBm, the bit-
error-ratio will be better than
1 x 10
-10
. As the input power is
decreased by several dB, the bit-
error-ratio degrades. Within 1 dB
below the 1 x 10
-2
BER input
optical power level, the CDR will
begin to lose lock and the clock
frequency will drift from 155.52
MHz. Once the CDR loses lock,
the clock frequency will sweep
through the entire VCO range,
about 140 to 200 MHz. The rate
of the sweep is inversely propor-
tional to the input optical power
and will reach its maximum at a
point of 2 dB below the lock
point. Since data is retimed to the
clock, a loss of lock will produce
an output data stream consisting
of randomly switching data bits,
i.e., noise.
Receiver Signal Detect
As the input optical power is
decreased, Signal Detect will
switch from high to low (de-
assert point) at a point between
3 dB below minimum guaranteed
sensitivity and the no light input
level. As the input optical power
is increased from very low levels,
Signal Detect will switch back
from low to high (assert point).
The assert level will be at least
0.5 dB higher than the de-assert
level. This single-ended low-
power PECL output is designed
to drive a standard PECL input
using a 10 kΩ load instead of the
normal 50
Ω
PECL load.
Reference Clock
In applications where the receiver
recovered clock frequency is not
allowed to drift upon loss of input
optical signal, the HFCT-5202
has the ability to generate a local
clock output by multiplying an
optional, external 19.44 MHz
reference clock up to the
OC-3/STM1 155.52 MHz rate.
This feature is possible because
the clock recovery system
consists of two loops: a data loop
which locks onto the incoming
optical data stream, and a second
reference loop which locks onto
the optional external reference
clock.
This optional feature is initiated
by applying a Lock-to-Reference
logic signal to pin 2 (Lck Ref-)
which switches the loop to the
external reference clock and
disables the received data
outputs. Pin 2 (Lck Ref-) can be
driven from the Signal Detect pin
15 (SD) output or from other
logic further upstream in the
ATM interface which may be
monitoring the quality of the
received data stream.
Transceiver Specified for
Wide Temperature Range
Operation
The HFCT-5202 is specified for
operation over normal commer-
cial temperature range of 0° to
+70°C (HFCT-5202B/D) or the
extended temperature range of
–40°C to +85°C (HFCT-5202A/C).
Other Members of HP
155 Mb/s Product Family
• HFCT-5205, 1300 nm laser-
based 1 x 9 SC receptacle
transceiver for 15 km links with
SMF cables (without CDR)
• HFBR-5208 1300 nm LED
based 1 x 9 SC receptacle
transceiver for 500 m links with
MMF cables (drop in
replacement for HFCT-5205)
• XMT5370-155 1300 nm laser-
based transmitter in pigtailed
package for 15 km links with
SMF cables
• XMT5170-155 1300 nm laser-
based transmitter in pigtailed
package for 40 km links with
SMF cables
• RCV1201D-155 receiver in
pigtailed package for 15 km
and 40 km links with SMF
cables
• RGR1551 receiver with integral
clock and data recovery in
pigtailed packages for 15 km
Applications Information
Typical BER Performance of
Receiver versus Input Optical
Power Level
The HFCT-5202 transceiver can
be operated at Bit-Error-Rate
conditions other than the
required BER = 1 x 10
-10
of the
ATM Forum 155.52 Mb/s Physical
Layer Standard. The typical
tradeoff of BER versus Relative
Input Optical Power is shown in
Figure 3. The Relative Input
Optical Power in dB is referenced
to the Input Optical Power
parameter value in the Receiver
Optical Characteristics table. For
10
-2
10
-3
LINEAR EXTRAPOLATION
OF 10
-4
THROUGH 10
-7
DATA POINTS
ACTUAL DATA
POINTS
BIT ERROR RATIO
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
-5
-4
-3
-2
-1
0
1
2
3
RELATIVE INPUT OPTICAL POWER – dBm avg.
Figure 3. Relative Input Optical
Power–dBm Avg.
4
better BER condition than
1 x 10
-10
, more input signal is
needed (+dB).
Recommended Circuit
Schematic
In order to insure proper
functionality of the HFCT-5202 a
recommended circuit is provided
in Figure 4. When designing the
circuit interface, there are a few
fundamental guidelines to follow.
For example, in the Recom-
mended Circuit Schematic figure
the differential data lines should
be treated as 50 ohm Microstrip
or stripline transmission lines.
This will help to minimize the
parasitic inductance and capaci-
tance effects. Proper termination
of the differential data and clock
signals will prevent reflections
and ringing which would
compromise the signal fidelity
and generate unwanted electrical
noise. Locate termination at the
received signal end of the
transmission line. The length of
these lines should be kept short
and of equal length to prevent
pulse-width distortion and data-
to-clock timing skew from
occurring. For the high speed
signal lines, differential signals
should be used, not single-ended
signals, and these differential
signals need to be loaded sym-
metrically to prevent unbalanced
currents from flowing which will
cause distortion in the signal.
Maintain a solid, low inductance
ground plane for returning signal
currents to the power supply.
Multilayer plane printed circuit
board is best for distribution of
V
CC
, returning ground currents,
forming transmission lines and
shielding. Also, it is important to
suppress noise from influencing
the fiber-optic transceiver
performance, especially the
receiver and the clock recovery
circuits. Proper power supply
filtering of V
CC
for this
transceiver is accomplished by
using the recommended, separate
filter circuits shown in Figure 4,
the Recommended Circuit
Schematic diagram, for the
transmitter and receiver sections.
These filter circuits suppress V
CC
noise of 50 mV peak-to-peak or
less over a broad frequency
range. This prevents receiver
sensitivity degradation as well as
false-lock or loss-of-lock in the
clock recovery circuitry due to
V
CC
noise. It is recommended
that surface-mount components
be used. Use tantalum capacitors
for the 10
µF
capacitors and
monolithic, ceramic bypass
capacitors for the 0.1
µF
Rx
Tx
NO INTERNAL
CONNECTION
NO INTERNAL
CONNECTION
HFCT-5202
TOP VIEW
TERMINATE
AT CLOCK
INPUTS
V
CC
C7
R13
R11
REF
CLK
R14
Rx
V
EE
18
RD
17
RD
16
SD
15
Rx
V
CC
14
Tx
V
CC
13
TD
12
TD
11
Tx
V
EE
10
LCK
REF CLK REF CLK
1
2
3
CLK
4
L
MON
L
MON
(-)
(+) T
XDIS
5*
7*
6*
NC
8*
P
MON
9*
R9
OPTIONAL
CLK
CLK
C8
R10
R12
C1
C2
V
CC
L1
TERMINATE
AT THE
DEVICE
INPUTS
R6
V
CC
R5
R7
C3
L2
C4
R2
R1
R3
R4
C5
C6
R8
R15
LOCATE
FILTER
AT VCC
PINS
TERMINATE AT
FIBER-OPTIC
TRANSCEIVER
INPUTS
RD
RD
SD
VCC
TD
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE PECL SIGNALS.
R1 = R4 = R6 = R8 = R10 = R12 = R14 = 130
Ω.
R2 = R3 = R5 = R7 = R9 = R11 = R13 = 82
Ω.
C1 = C2 = C3 = C5 = C6 = C7 = 0.1 µF.
C4 = C8 = 10 µF.
L1 = L2 = 1 µH COIL.
R15 = 10 kΩ.
FOR THE SINGLE MODE HFCT-5202 TRANSCEIVER, PINS 5 - 9 ARE USED FOR LASER DIODE BIAS
AND OPTICAL POWER MONITORING AS WELL AS TO PROVIDE A TRANSMITTER DISABLE
FUNCTION. *FOR THE MULTIMODE HFBR-5207 TRANSCEIVER, PINS 5 - 9 ARE NOT USED.
Figure 4. Recommended Circuit Schematic.
5
capacitors. Also, it is recom-
mended that a surface-mount coil
inductor of 1
µH
be used. Ferrite
beads can be used to replace the
coil inductors when using quieter
V
CC
supplies, but a coil inductor
is recommended over a ferrite
bead. Coils with a low, series dc
resistance (<0.7 ohms) and high,
Self-resonating frequency are
recommended. All power supply
components need to be placed
physically next to the V
CC
pins of
the receiver and transmitter. Use
a good, uniform ground plane
with a minimum number of holes
to provide a low-inductance
ground current return for the
power supply currents.
In addition to these recommenda-
tions, Hewlett-Packard’s Applica-
tion Engineering staff is available
for consulting on best layout
practices with various vendors
mux/demux, clock generator and
clock recovery circuits. HP has
participated in several reference
design studies and is prepared to
share the findings of these
studies with interested customers.
Contact your local HP sales
representative to arrange for this
service.
Evaluation Circuit Boards
Evaluation circuit boards
implementing this recommended
circuit design are available from
Hewlett-Packard’s Application
Engineering staff. Contact your
local HP sales representative to
arrange for access to one if
needed.
Operation in -5.2 V Designs
For applications that require
-5.2 V dc power supply level for
true ECL logic circuits, the
HFCT-5202 transceiver can be
operated with a V
CC
= 0 V dc and
a V
EE
= -5.2 V dc. This
transceiver is not specified with
an operating, negative power
supply voltage. The potential
compromises that can occur with
use of -5.2 V dc power are that
the absolute voltage states for
V
OH
and V
OL
will be changed
slightly due to the 0.2 V differ-
ence in supply levels. Also, noise
immunity may be compromised
for the HFCT-5202 transceiver
because the ground plane is now
the V
CC
supply point. The
suggested power supply filter
circuit shown in Figure 4
Recommended Circuit Schematic
should be located in the V
EE
paths at the transceiver supply
pins. Direct coupling of the
differential data and clock signals
can be done between the HFCT-
5202 transceiver and the
standard ECL circuits. For
guaranteed -5.2 V dc operation,
contact your local Hewlett-
Packard Field Sales Engineer for
assistance.
Recommended Solder Fluxes
and Cleaning/Degreasing
Chemicals
Solder fluxes used with the
HFCT-5202 fiber-optic
transceiver should be water-
soluble, organic solder fluxes.
Some recommended solder fluxes
are Lonco 3355-11 from London
Chemical West, Inc. of Burbank,
CA, and 100 Flux from Alpha-
metals of Jersey City, N.J.
Recommended cleaning and
degreasing chemicals for the
HFCT-5202 are alcohols (methyl,
isopropyl, isobutyl), aliphatics
(hexane, heptane), and other
chemicals, such as soap solution
or naphtha. Do not use partially
halogenated hydrocarbons for
cleaning/degreasing. Examples of
chemicals to avoid are 1.1.1.
trichloroethane, ketones (such as
MEK), acetone, chloroform, ethyl
acetate, methylene dichloride,
phenol, methylene chloride, or
N-methylpyrolldone.
Regulatory Compliance
The HFCT-5202 is intended to
enable commercial system
designers to develop equipment
that complies with the various
regulations governing certifica-
tion of Information Technology
Equipment. See the Regulatory
Compliance Table 1 for details.
Additional information is
available from your Hewlett-
Packard sales representative.
Electrostatic Discharge (ESD)
Normal ESD handling precautions
for ESD sensitive devices should
be followed while using the
HFCT-5202. These precautions
include using grounded wrist
straps, work benches, and floor
mats in ESD controlled areas.
Recommended Solder and
Wash Process
The HFCT-5202 is compatible
with industry standard wave or
hand solder processes.
HFCT-5202 Process Plug
The HFCT-5202 transceiver is
supplied with a process plug for
protection of the optical ports
with the Duplex SC connector
receptacle. This process plug
prevents contamination during
wave solder and aqueous rinse as
well as during handling, shipping,
or storage. It is made of high-
temperature, molded, sealing
material that will withstand
+80°C and a rinse pressure of
50 lb/in
2
.
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