HM628128D Series
1 M SRAM (128-kword
×
8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword
×
8-bit. HM628128D
Series has realized higher density, higher performance and low power consumption by employing Hi-
CMOS process technology. The HM628128D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,
standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
•
Single 5 V supply: 5 V
±
10%
•
Access time: 55 ns/70 ns (max)
•
Power dissipation
Active: 30 mW/MHz (typ)
Standby: 10
µW
(typ)
•
Completely static memory.
No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output
Three state output
•
Directly TTL compatible all inputs
•
Battery backup operation
2 chip selection for battery backup
HM628128D Series
Ordering Information
Type No.
HM628128DLP-5
HM628128DLP-7
HM628128DLP-5SL
HM628128DLP-7SL
HM628128DLP-5UL
HM628128DLP-7UL
HM628128DLFP-5
HM628128DLFP-7
HM628128DLFP-5SL
HM628128DLFP-7SL
HM628128DLFP-5UL
HM628128DLFP-7UL
HM628128DLTS-5
HM628128DLTS-7
HM628128DLTS-5SL
HM628128DLTS-7SL
HM628128DLTS-5UL
HM628128DLTS-7UL
HM628128DLT-5
HM628128DLT-7
HM628128DLT-5SL
HM628128DLT-7SL
HM628128DLT-5UL
HM628128DLT-7UL
HM628128DLR-5
HM628128DLR-7
HM628128DLR-5SL
HM628128DLR-7SL
HM628128DLR-5UL
HM628128DLR-7UL
Access time
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
Reverse-bend type 8
×
20 mm 32-pin plastic TSOP I (TFP-32DR)
Normal-bend type 8
×
20 mm 32-pin plastic TSOP I (TFP-32D)
8
×
13.4 mm 32-pin plastic TSOP I (TFP-32DC)
525-mil 32-pin plastic SOP (FP-32D)
Package
600-mil 32-pin plastic DIP (DP-32)
2
HM628128D Series
Pin Arrangement
32-pin DIP/SOP
32-pin TSOP (Normal Type TSOP)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
A11
A9
A8
A13
WE
CS2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-pin TSOP (Reverse Type TSOP)
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CS2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
Pin Description
Pin name
A0 to A16
I/O0 to I/O7
CS1
CS2
WE
OE
V
CC
V
SS
NC
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Power supply
Ground
No connection
3
HM628128D Series
Block Diagram
LSB
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
MSB
Row
decoder
•
•
•
•
•
V
CC
V
SS
Memory matrix
512 x 2,048
I/O0
Input
data
control
I/O7
•
•
Column I/O
Column decoder
•
•
LSB
A14 A16 A15 A13 A8 A9 A11
•
•
MSB
CS1
CS2
WE
OE
Timing pulse generator
Read/Write control
4
HM628128D Series
Operation Table
CS1
H
L
L
L
L
L
L
CS2
H
L
L
H
H
H
H
WE
×
×
×
H
L
L
H
OE
×
×
×
L
H
L
H
I/O
High-Z
High-Z
High-Z
Dout
Din
Din
High-Z
Operation
Standby
Standby
Standby
Read
Write
Write
Output disable
Note: H: V
IH
, L: V
IL
,
×:
V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Terminal voltage on any pin relative to V
SS
Power dissipation
Storage temperature range
Storage temperature range under bias
Symbol
V
CC
V
T
P
T
Tstg
Tbias
Value
–0.5 to +7.0
–0.5*
1
to V
CC
+ 0.3*
2
1.0
–55 to +125
–20 to +85
Unit
V
V
W
°C
°C
Notes: 1. V
T
min: –1.5 V for pulse half-width
≤
30 ns
2. Maximum voltage is +7.0 V
DC Operating Conditions
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Ambient temperature range
Note:
V
IH
V
IL
Ta
Min
4.5
0
2.2
–0.3
–20
Typ
5.0
0
—
—
—
Max
5.5
0
V
CC
+ 0.3
0.8
+70
Unit
V
V
V
V
°C
1
Note
1. V
IL
min: –1.5 V for pulse half-width
≤
30 ns
5
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