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www.fairchildsemi.com
TMC1175A
Video A/D Converter
8 bit, 40 Msps
Features
•
•
•
•
•
•
•
•
•
•
8-Bit resolution
40 Msps conversion rate
Low power: 100mW at 20 Msps
Integral track/hold
Integral and differential linearity error 0.5 LSB
Single or dual +5 Volt supplies
Differential phase 0.5 degree
Differential gain 1.5%
Three-state TTL/CMOS-compatible outputs
Low cost
Description
The TMC1175A analog-to-digital (A/D) converter employs
a two-step flash architecture to convert analog signals into
8-bit digital words at sample rates of up to 40 Msps
(Megasamples per second). An integral Track/Hold circuit
delivers excellent performance on signals with full-scale fre-
quency components up to 12 MHz. Innovative architecture
and submicron CMOS technology limit typical power dissi-
pation to 100 mW.
Power may be derived from either single or dual +5V
supplies. Internal voltage reference resistors allow self-bias
operation. Input capacitance is very low, simplifying or
eliminating input driving amplifiers. All digital three-state
outputs are TTL- and CMOS-compatible.
The TMC1175A is available in 24-lead plastic SOIC, and
28-lead J-lead PLCC packages. Performance specifications
are guaranteed from -20°C to 75°C.
Applications
•
•
•
•
•
•
•
Video digitizing
VGA and CCD digitizing
LCD projection panels
Image scanners
Personal computer video boards
Multimedia systems
Low cost, high speed data conversion
Block Diagram
V
IN
Track/
Hold
Coarse
Quantizer
VR+
R
T
R
B
VR–
Reference
Matrix
Digital
Error-
Corrector
D
7-0
Fine
Quantizer
OE
CONV
24453A
REV. 1.3.3 2/28/02
TMC1175A
PRODUCT SPECIFICATION
Functional Description
The TMC1175A 8-bit A/D converter uses a two-step archi-
tecture to perform analog-to-digital conversion at rates up to
40 Msps. The input signal is held in an integral track/hold
stage during the conversion process. Operation is pipelined,
with one input sample taken and one output word provided
for each CONVert cycle.
The first step in the conversion process is a coarse 4-bit
quantization. This determines the range of the subsequent
fine 4-bit quantization step. To eliminate spurious codes, the
fine 4-bit A/D quantizer output is gray-coded and converted
to binary before it is combined with the coarse result to form
a complete 8-bit result.
V DDA
VR+
+2.6V
R
T
R+
324Ω
RREF
270Ω
R
B
+0.6V
VR–
R–
81Ω
Analog Input and Voltage References
The TMC1175A converts analog signals in the range R
B
to
R
T
into digital data. Input signals outside that range produce
“saturated” 00h or FFh output codes. The device will not be
damaged by signals within the range A
GND
to V
DDA
.
Input voltage range is very flexible and extends from the +5
Volt power supply to ground. Performance is specified over
the optimom 2 volt input range: 0.6V to 2.6V. However, the
part will function with a full-scale range from 1.0V to 5.0V.
A reduced input range may simplify analog signal condition-
ing circuitry, at the expense of additional noise sensitivity
and reduced differential linearity. Increasing the range can
improve differential linearity, but imposes a greater burden
on the input signal conditioning circuitry.
In many applications, external voltage reference sources are
connected to the R
T
and R
B
pins. R
B
can be grounded. Gain
and offset errors are directly related to the accuracy and sta-
bility of the applied reference voltages.
Two reference pull-up and pull-down resistors connected to
VR+ and VR– are provided internally for operation without
external voltage reference circuitry (Figure 1). The reference
voltages applied to R
T
and R
B
may be generated by connect-
ing VR+ to R
T
and VR- to R
B
. The power supply voltage is
divided by the on-chip resistors to bias the R
T
and R
B
points.
This sets-up the converter for operation in its nominal range
from 0.6V to 2.6V.
27010A
Figure 1. Reference Resistors
With V
DDA
at 5.0V, connecting VR+ to R
T
and grounding
R
B
will provide an input range from 0.0V to 2.27V, while
connecting R
T
to V
DDA
and R
B
to VR- produces a full scale
range of 3.85V referenced to V
DDA
. External resistors may
also be employed to provide arbitrary reference voltages, but
they will not match the temperature coefficient of the on-
chip resistors as well as R+ and R-, and will cause the con-
verter transfer function to vary with temperature.
With this implementation, errors in the power supply voltage
end up on the conversion data output.
Because a two-step conversion process is employed, it is
important that the references remain stable during the
ENTIRE conversion process (two clock cycles). The refer-
ence voltage can then be changed, but any conversion in
progress during a reference change is invalid.
2
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Table 1. Output Coding
Input Voltage
R
T
+ 1 LSB
R
T
R
T
– 1 LSB
•••
R
B
+ 128 LSB
R
B
+ 127 LSB
•••
R
B
+ 1 LSB
R
B
R
B
– 1 LSB
Note:
1. LSB = (R
T
– R
B
) / 255
Output
FF
FF
FE
•••
80
7F
•••
01
00
00
remain valid for t
HO
(Output Hold Time), satisfying any
hold time requirement of the receiving circuit. The new data
become valid t
DO
(Output Delay Time) after this rising edge
of CONV.
The outputs of the TMC1175A are CMOS- and TTL-com-
patible, and are capable of driving four low-power Schottky
TTL (54/74LS) loads. An Output Enable control, OE, places
the outputs in a high-impedance state when HIGH. The out-
puts are enabled when OE is LOW.
Power and Ground
To minimize noise injection into the analog section, V
DDA
may be connected to a separate regulated +5 volt supply.
V
DDD
may be connected to a digital supply. Power up
sequence is immaterial. Latch-up will not occur.
A
GND
and D
GND
pins should be connected to a common
ground plane. For optimum performance treat analog and
digital PWB traces as transmission lines. Route analog
connections cleanly to the TMC1175A. Segregate digital
connections and if necessary terminate clocks to eliminate
ringing. Prevent digital returm currents from flowing across
analog input sections of the TMC1175A.
Digital Inputs and Outputs
Sampling of the applied input signal takes place on the
fall-
ing
edge of the CONV signal (Figure 2). The output word is
delayed by 2 1/2 CONV cycles. It is then available after the
rising
edge of CONV. The previous data on the output
t
STO
Sample N
V
IN
Sample N+1
t
PWL
CONV
t
DO
t
HO
D
7-0
ORP
ORN
Hi-Z
Data N–3
Data N–2
Data N–1
t
PWH
1/f
S
Sample N+2
Sample N+3
Data N
t
DIS
t
ENA
OE
24455A
Figure 2. Conversion Timing
REV. 1.3.3 2/28/02
3
TMC1175A
PRODUCT SPECIFICATION
V(1)
V(2)
V(3)
V(4)
Analog input
External Clock
S (1)
C (1) S (2)
C (2) S (3)
C (3)
S (4) C (4)
MD (3)
Upper comparators block
Upper data
MD (0)
MD (1)
MD (2)
Lower reference voltage
RV (0)
RV (1)
RV (2)
RV (3)
Lower comparators A block
S (1)
H (1)
LD (-1)
C (1)
S (3)
H (3)
LD (1)
C (3)
Lower data A
Lower comparators B block
Lower data B
H (0)
LD(-2)
C (0)
S (2)
H (2)
LD(0)
C (2)
S (4)
H (94)
LD(2)
Digital output
Out(-2)
Out(-1)
Out(0)
Out(1)
65-7568
Figure 3. Internal Timing
Pin Assignments
OE
D
GND
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
V
DDD
CONV
1
2
3
4
5
6
7
8
9
10
11
12
M7 Package
24
23
22
21
20
19
18
17
16
15
14
13
D
GND
R
B
VR–
A
GND
A
GND
V
IN
V
DDA
R
T
VR+
V
DDA
V
DDA
V
DDD
25
24
23
22
21
20
19
18
17
16
15
14
13
A GND
A GND
VIN
N/C
VDDA
RT
VR+
VR– 26
R
B
27
D
GND
28
N/C 1
OE 2
D
GND
3
D
0
4
D1 5
D2 6
D3 7
N/C 8
D4 9
D5 10
D6 11
V
DDA
V
DDA
V
DDD
N/C
CONV
V
DDD
12 D
7
R3 Package
24454A
4
REV. 1.3.3 2/28/02
嵌入式系统
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