INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT30
8-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-input NAND gate
FEATURES
•
Output capability: standard
•
I
CC
category: SSI
GENERAL DESCRIPTION
74HC/HCT30
The 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT30 provide the 8-input NAND function.
QUICK REFERENEC DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay A, B, C, D, E, F, G, H to Y
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
3.5
15
HCT
12
3.5
15
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-input NAND gate
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
9, 10, 13
11
12
14
SYMBOL
A
B
C
D
E
F
GND
Y
n.c.
G
H
V
CC
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
data input
data input
positive supply voltage
NAME AND FUNCTION
74HC/HCT30
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
Fig.4
Functional diagram;
Y = ABCDEFGH.
Fig.5 Logic diagram.
FUNCTION TABLE
INPUTS
A
L
X
X
X
X
X
X
X
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
B
X
L
X
X
X
X
X
X
H
C
X
X
L
X
X
X
X
X
H
D
X
X
X
L
X
X
X
X
H
E
X
X
X
X
L
X
X
X
H
F
X
X
X
X
X
L
X
X
H
G
X
X
X
X
X
X
L
X
H
H
X
X
X
X
X
X
X
L
H
OUTPUT
Y
H
H
H
H
H
H
H
H
L
December 1990
4
Philips Semiconductors
Product specification
8-input NAND gate
DC CHARACTERISTICS FOR 74 HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
74HC/HCT30
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+
85
−40
to
+125
UNIT V
CC
(V)
ns
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
TEST CONDITIONS
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
A, B, C, D, E, F, G, H to Y
output transition time
41
15
12
19
7
6
130
26
22
75
15
13
165
33
28
95
19
16
195
39
33
110
22
19
Fig.6
t
THL
/ t
TLH
ns
Fig.6
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
A, B, C, D, E, F, G, H
UNIT LOAD COEFFICIENT
0.60
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HCT
SYMBOL
PARAMETER
+25
−40
to
+
85
−40
to
+125
UNIT V
CC
(V)
WAVEFORMS
TEST CONDITIONS
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
t
THL
/ t
TLH
propagation delay
A, B, C, D, E, F, G, H to Y
output transition time
16
7
28
15
35
19
42
22
ns
ns
4.5
4.5
Fig.6
Fig.6
December 1990
5
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