Gray Scale Font Engine IC
MN55720
Gray Scale Font Engine
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Overview
The MN55720 is a high-quality character generator IC that rapidly generates multilevel grayscale data from outline
(path) data for characters and similar images. This IC includes input and output FIFO memory units to assure high-
speed processing, and provides a local interface (16 or 32 bits) to allow the use of this IC in a wide range of equipment.
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Features
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Applications
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STB and DTV
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Block Diagrams
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RAM
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MN55720
Bus-bridge
Local Bus
ROM
CPU
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1
•
Package:
Publication date: June 2002
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Gray scale levels:
•
Bit sizes:
•
Interface specifications:
•
Operating frequency:
•
Operating supply voltage:
Can be set to any level from 2 to 128 levels.
Can generate characters of any size.
Local bus (Supports both 16-bit and 32-bit busses.)
50 MHz to 70 MHz
External supply: 3.3 V±0.3 V
Internal supply: 2.5 V±0.2 V
80 pin TQFP (12 mm
×
12 mm)
MN55720
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Pin Assignments
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D9
D10
D11
VSS
VDD3
D12
D13
D14
D15
VSS
VDD3
D16
D17
VSS
VDD2
D18
D19
VSS
VDD3
D20
U
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2
TEST
OCLOCK
VDD2
VSS
MINTEST
CLKSEL
NRST
BUSSEL
VDD3
HOSTCLK
VSS
AVSS
TCPOUT
AVDD
PLLON
AD2
AD1
AD0
IRQ
NWE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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(TOP VIEW)
SDF00027AEM
D8
VDD3
VSS
VDD2
D7
D6
D5
D4
VDD3
VSS
D3
D2
D1
D0
VSS
LON
VDD3
VDDREG
REGOUT
VSS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
D21
D22
D23
VSS
VDD3
D24
D25
D26
D27
VSS
VDD3
D28
D29
D30
D31
VDD2
VSS
VDD3
NCS
NRE
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MN55720
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Pin Descriptions
1) Local 32-bit mode
Pin
HOSTCLK
NRST
AD[2:0]
NCS
NWE
NRE
D[31:0]
IRQ
BUSSEL
CLKSEL
MINTEST
TEST
PLLON
OCLOCK
TCPOUT
LON
VDD3
VDDREG
REGOUT
VDD2
VSS
AVDD
AVSS
I/O
I
I
I
I
I
I
I/O
O
I
I
I
I
I
O
O
I
I
I
O
I
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Clock input from the host
Hardware reset (active low)
Address signal from the host
Chip select signal from the host (active low)
Write enable signal from the host (active low)
Read enable signal from the host (active low)
Data I/O (32-bit)
Interrupt output to the host (active high)
Description
Data bus width setting (Must be held fixed at the high level)
Clock selection (0: Low-speed clock used, 1: High-speed clock used)
Test pin
Test pin
Test pin
Test pin
Test pin
Note) 1. Connect the MINTEST pin to ground.
2. The NRST (hardware reset) signal pulse width must be at least 100 ns.
2) Local 16-bit mode
Pin
I/O
I
I
I
I
I
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I/O
I/O
Clock input from the host
Hardware reset (active low)
Address signal from the host
Chip select signal from the host (active low)
Write enable signal from the host (active low)
Read enable signal from the host (active low)
Unused (These lines output fixed low-level signals.)
Data I/O (16-bit)
Description
HOSTCLK
NRST
AD[2:0]
NCS
NWE
NRE
D[31:16]
D[15:0]
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Regulator control (active high)
3.3 V system power supply (I/O)
3.3 V power supply (regulator)
Regulator output (2.5 V)
PLL system analog ground
2.5 V system power supply (internal logic circuits)
Common ground for I/O and internal logic circuits
PLL system analog power supply (3.3 V)
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MN55720
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Pin Descriptions (continued)
2) Local 16-bit mode (continued)
Pin
IRQ
BUSSEL
CLKSEL
MINTEST
TEST
PLLON
OCLOCK
TCPOUT
LON
VDD3
VDDREG
REGOUT
VDD2
VSS
AVDD
AVSS
I/O
O
I
I
I
I
I
O
O
I
I
I
O
I
I
Description
Interrupt output to the host (active high)
Data bus width setting (Must be held fixed at the high level)
Clock selection (0: Low-speed clock used, 1: High-speed clock used)
Test pin
Test pin
Test pin
Test pin
Test pin
Regulator control (active high)
3.3 V system power supply (I/O)
3.3 V power supply (regulator)
Regulator output (2.5 V)
2.5 V system power supply (internal logic circuits)
Common ground for I/O and internal logic circuits
PLL system analog power supply (3.3 V)
Note) 1. Connect the MINTEST pin to VSS.
2. The NRST (hardware reset) signal pulse width must be at least 100 ns.
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Power supply
2. Using the regulator
The MN55720 includes a built-in 2.5 V output regulator, which allows this device to function as a single 3.3 V power
supply IC. However, since the voltage drop in the regulator is 0.8 V, the power consumption in just the regulator will
be 80 mW when the IC draws 100 mA.
If a 2.5 V level is provided externally and the regulator is not used, provide a 3.3 V level to VDDREG as shown in
the figure below.
Note that the 2.5 V regulator output cannot be used to supply other devices.
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U
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1. Power on and off sequences
Do not apply power to one of the VDD2 and VDD3 supplies without applying power to the other at the same time.
Failing to observe this may cause the problems listed below. The internal logic power supply VDD2 and the external
I/O power supply VDD3 should be applied and cut as close to simultaneously as possible.
•
Degradation of I/O block devices
•
Inability to establish the states of the output and bidirectional pins even by setting NRST low.
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PLL system analog ground
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MN55720
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Power supply (continued)
2. Using the regulator (continued)
1) When using the regulator output to supply a 2.5 V level
LON VDDREG
REGOUT
VDD2
VDD2
VDD2
VDD2
10
µF
3.3 V
2) When supplying the 2.5 V level externally
LON VDDREG
REGOUT
VDD2
3.3 V
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Functional Description
1. Register memory addresses
1) Memory address map
AD2
0
0
AD1
0
0
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AD0
0
1
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Open
2.5 V
NAME
POINT
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VDD2
VDD2
Content
Outline data input port
Grayscale data output port
RASTER
2) Register address map
U
AD2
0
0
1
1
AD1
1
1
0
0
AD0
0
1
0
1
NAME
PSTATUS
RSTATUS
CONTROL
Content
POINT FIFO status
RASTER FIFO status
Control register
VAL_LEVEL Level value conversion register
3) Other items
AD2
1
AD1
1
AD0
0
NAME
SRESET
Content
Software reset
R/W
W
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VDD2
R/W
W
R
R/W
R
R
R/W
R/W
SDF00027AEM
5
stm32/stm8
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