MX93111
MX93111 DATA SHEET
CONTENT
1 INTRODUCTION
1.1 FEATURE
1.2 DIFFERENCE BETWEEN MX93011C AND MX93111
2
3
4
6
9
9
10
13
18
23
28
34
35
36
44
47
49
50
2 PIN
2.1
2.2
2.3
2.4
2.5
3.1
3.2
3.3
3.4
4.1
4.2
4.3
4.4
PIN OUT FOR 128 PIN PQFP MX93111
PIN DESCRIPTIONS
PIN TYPE ABBREVIATION
PINS SUMMARY BY PIN TYPE
MULTIPLEX PINS
DATA UNIT
MEMORY MAP AND ADDRESSING MODES
PROGRAM FLOW CONTROL UNIT
APPLICATION INTERFACE UNIT
I/O MAPPED REGISTERS SUMMARY
NON I/O MAPPED REGISTER SUMMARY
I/O MAPPED REGISTERS DESCRIPTION
NON I/O MAPPED REGISTER DESCRIPTION
3 ARCHITECTURE
4 REGISTERS
5 INSTRUCTIONS
5.1 INSTRUCTION SET SUMMARY
5.2 ACRONYMS AND NOTATIONS
5.3 INSTRUCTION SET DESCRIPTION
6 PCM CODEC
6.1 PCM CODEC OVERVIEW
6.2 FUNCTIONAL DESCRIPTION
6.3 CONTROL REGISTERS DEFINITION
85
88
93
97
102
117
117
7 CHARACTERISTICS
7.1 DC CHARACTERISTICS
7.2 AC TIMING AND CHARACTERISTICS
8 PACKAGE INFORMATION
8.0 ORDERING INFORMATION
8.1 PACKAGE INFORMATION FOR 128 PIN PQFP
1
Ver 0.01, December 5, 2000
MX93111
1.1 FEATURES
¡ »
Optimized for highly integrated digital answering machine application
¡ »
Built in DRAM controller; interface with x1,x4, x8 and x16 configuration
¡ »
8 bits host interface
One
¡ »
Maximum 9 general input pins , 23 output pins and 8 programmable bi-directional I/O pins
¡ »
external interrupt pins
One
¡ »
internal timer interrupt
1ms
¡ »
K words program space, 48 K internal , in which control code and voice prompt can be built
64
¡ »
K words data space , 2.5 K words data RAM internal
64
¡ »
MHz running clock , provide 30 MIPs processing power with 40 mA active current
45
¡ »
Built in PLL with 4.096 MHz clock as clock source to achieve 2 mA consumption in power down
mode
operation
¡ »
x 16 multiplication and 32 bit accumulation executed in one instruction cycle
16
¡ »
Single cycle normalization instruction
¡ »
bit barrel shifter with left/right shift 15 bits capability
32
¡ »
level hardware stack
32
¡ »
Auxiliary registers used in register indirect addressing.
8
¡ »
Zero-overhead hardware looping , maximum 8 instruction words executed repeatedly 1024 times
maximum
¡ »
Built-in one PCM CODEC
¡ »
CODECs support 16-bit format linear data
¡ »
Support switch paths for DAM (digital answering machine) related applications
¡ »
Support two comparators for power-low and battery -low detection
¡ »
Support external L..P.F. for D/A output path
¡ »
Support external volume control
¡ »
On-chip differential line driver
¡ »
On-chip ALC (automatic level control)
¡ »
On-chip digital volume control of CODEC
¡ »
On-chip programmable receive/transmit gain control of CODEC
¡ »
interface to FAX or cordless Phone
Easy
¡ »
Fabricated in 0.5 um 5V CMOS process
¡ »
pins PQFP package
128
2
Ver 0.01, December 5, 2000
MX93111
1.2 DIFFERENCE between MX93011C and MX93111
MX93011C
INTERNAL RAM
SIZE
2K Words
Bank0 : 0x0000 ~ 0x03FF(1K)
Bank1 : 0x0400 ~ 0x07FF(1K)
0X0800
MX93111
2.5K Words
Bank0 : 0x0000 ~ 0x03FF(1K)
Bank1 : 0x0400 ~ 0x09FF(1.5K)
0X1000
48k Words
0XC000
10-BIT
10-BIT
No
Fix continuous “ SQRA”
EXTERNAL RAM
STARTING ADDRESS
INTERNAL ROM
32k Words
SIZE
EXTERNAL ROM
STARTING ADDRESS
REPEAT COUNT
REGISTER
AR MODULO
REGISTER
INTERRUPT PENDING
STATUS REGISTER
CONTINUOUS
INSTRUCTION
“SQRA”
EXTENDED OUTPUT
PORT REGISTER
CODEC COMMAND
REGISTER
CODEC
RECEIVE/TRANSMIT
REGISTERS
CODEC INTERFACE
X’ TAL source
FLL Multiplication
Factor Register
(FLLMR)
FLL Control Register
(FLLCONR)
FLL Status Register
(FLLSR)
CMCK Divide Ratio
Register
(CMCKDIVR)
0X8000
7-BIT
7-BIT
REG5 (R)
Overflow problem
OPT21 – OPT19
No
REG16(R) : CDRR0
REG17(W) : CDXR0
Single external codec
interface
32.256MHz & 32.768KHz
13-Bit (0 – 0x1FFF)
OPT22 – OPT19
REG5(R/W)
REG16(R/W): CDDR0, CDXR0
Single built-in internal codec
4.096MHz
5-Bit (12 – 24)
12-Bit
13-Bit
5-Bit
No
No
No
3
Ver 0.01, December 5, 2000
MX93111
2.1 PIN OUT for 128 PIN PQFP MX93111
PGAC2
ALCRC
PGAC1
FLLEN\
128
SVDD1
SVDD2
ALCC2
ALCC1
LPFC2
LPFC1
EROM
127
AGND
125
SGND
AVDD
124
SPKN
SPKP
VREF
AUX2
AUX1
RST\
126
VBG
FILT
MIC
LIN
AG
VR
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
ED15
ED14
ED13
ED12
ED11
ED10
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
GND
OPT22
CAS\/OPT21
DRD\/OPT20
DWR\/OPT19
RAS\/IPT8
VDD
GND
EDCE\
EPCE\
ERD\
EWR\
EAD15
EAD14
EAD13
EAD12
EAD11
EAD10
EAD9
EAD8
EAD7
EAD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
AGND
AVDD
LOUTN
LOUTP
CMP1I
CMP1O
CMP2I
CMP2O
VCOMP
GND
TEST1\
TEST0\
HOLD\
HDB0/BIO0
HDB1/BIO1
HDB2/BIO2
HDB3/BIO3
GND
VDD
HDB4/BIO4
HDB5/BIO5
HDB6/BIO6
HDB7/BIO7
ACK\/XF\
HRD\/OPT17
HWR\/OPT16
HILO/OPT18
IPT7
IPT6
IPT5
IPT4
IPT3
IPT2
IPT1
IPT0
OPT0
OPT1
OPT2
MX93111
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
OPT3
XI
EAD5
EAD4
EAD3
EAD2
EAD1
EAD0
NMI\/TCLK
XO
INT1\
VDD
CP
OPT15
OPT14
OPT13
OPT12
OPT11
OPT10
GND
OPT9
OPT8
OPT7
OPT6
OPT5
4
Ver 0.01, December 5, 2000
OPT4
MX93111
2.2 PIN DESCRIPTIONS
1. POWER/CLOCK/CONTROL PINS :
Name
VDD
GND
FLLEN\
Pin Type
Power
Power
IS
Pin Number
23,47,84
24,51,85,93
17
128
Description
5 Volt power source pins
Ground pins
1 : Test X‘ tal mode.
0 : Single low X‘ tal mode. High clock will be generated from
FLL
4.096 MHz crystal oscillator‘ s input
4.096 MHz crystal oscillator‘ s output
Output of internal PLL charge pump circuit.
Power on reset pin.Minium timing 50ms.
Level trigger.Hold down clock to DSP (X‘ tal oscillator or FLL is
still active) and related data ,address and control pins will go to
high-impedance state.
Map all program memory space to external
Falling Edge-triggered non-maskable external interrupt / Test
clock in
Falling Edge-triggered maskable external interrupt
Test pin for CODEC
Test pin for CODEC
XI
XO
CP
RST\
HOLD\
X‘ tal
X‘ tal
I/O(A)
IS
IS
48
49
50
126
90
EROM
NMI\/TCLK
INT1\
TEST0\
TEST1\
IS
IS
IS
ISH
ISH
127
46
45
91
92
Note 1: FLLEN\,HOLD\,EROM,GND,NMI\/TCLK,INT1\,TEST0\,TEST1\ pin output low when DSP is in
reset state or in power down mode.
5
Ver 0.01, December 5, 2000
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