The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8 bits. It
is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 8/10/12/15/20 ns with output enable access times (t
OE
) of 5, 5, 6, 7, 8 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on
the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with
RXWSXW HQDEOH
OE
RU ZULWH HQDEOH
(WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common industry
standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–65
–55
–
Max
+5.0
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
o
o
C
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
Key: X = don’t care, L = low, H = high.
3/31/03, v. 042003
Alliance Semiconductor
P. 2 of 8
AS7C31025B
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
V
IL
min. = –3.0 V for pulse width less than t
RC
/2.
Symbol
V
CC
V
IH
V
IL†
T
A
T
A
Min
3.0
2.0
–0.5
0
–40
Nominal
3.3
–
–
–
–
Max
3.6
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
o
C
o
C
DC operating characteristics (over the operating range)
-8
Parameter
Input leakage
current
Output leakage
current
Operating power
supply current
-10
-12
-15
-20
Sym
|
I
LI
|
|
I
LO
|
I
CC
I
SB
Test conditions
V
CC
= Max, V
IN
= GND to V
CC
V
CC
= Max, CE = V
IH
,
V
out
= GND to V
CC
CE = V
IL
,
f
=
f
Max
,
I
OUT
= 0 mA
CE = V
IH
, f = f
Max
, f
OUT
= 0
CE
≥
V
CC
–0.2 V,
V
IN
≤
0.2 V or V
IN
≥
V
CC
–0.2 V,
f = 0, f
OUT
= 0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Min Max Min Max Min Max Min Max Min Max Unit
–
–
–
–
–
–
2.4
1
1
75
30
–
–
–
–
–
–
2.4
1
1
70
30
–
–
–
–
–
–
2.4
1
1
65
25
–
–
–
–
–
–
2.4
1
1
60
20
–
–
–
–
–
–
2.4
1
1
55
20
µA
µA
mA
mA
mA
V
V
Standby power
supply current
I
SB1
V
OL
V
OH
5
0.4
–
5
0.4
–
5
0.4
–
5
0.4
–
5
0.4
–
Output voltage
Capacitance (
f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL
)
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE
I/O
Test conditions
V
IN
= 0 V
V
IN
= V
OUT
= 0 V
Max
5
7
Unit
pF
pF
3/31/03, v. 042003
Alliance Semiconductor
P. 3 of 8
AS7C31025B
®
Read cycle (over the operating range)
-8
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE
ORZ W
o output in low Z
CE high to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
Power down time
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
8
–
–
–
3
3
–
0
–
0
–
–
8
8
5
–
–
3
–
4
–
8
-10
10
–
–
–
3
3
–
0
–
0
–
–
10
10
5
–
–
3
–
5
–
10
-12
12
–
–
–
3
3
–
0
–
0
–
–
12
12
6
–
–
3
–
6
–
12
-15
15
–
–
–
3
3
–
0
–
0
–
–
15
15
7
–
–
4
–
7
–
15
-20
20
–
–
–
3
3
–
0
–
0
–
–
20
20
8
–
–
5
–
8
–
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
3
Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
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