CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
D
2-V to 6-V V
CC
Operation (’HC190, 191)
D
4.5-V to 5.5-V V
CC
Operation (’HCT191)
D
Wide Operating Temperature Range of
D
D
D
D
D
D
−55°C to 125°C
Synchronous Counting and Asynchronous
Loading
Two Outputs for n-Bit Cascading
Look-Ahead Carry for High-Speed Counting
Balanced Propagation Delays and
Transition Times
Standard Outputs Drive Up To 15 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
CD54HC190, 191; CD54HCT191 . . . F PACKAGE
CD74HC190 . . . E, NS, OR PW PACKAGE
CD74HC191, CD74HCT191 . . . E OR M PACKAGE
(TOP VIEW)
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
description/ordering information
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and
CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous
parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up
(D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented
synchronously with the low-to-high transition of the clock.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
CD74HC190E
PDIP − E
Tube of 25
Tube of 40
Reel of 2500
SOIC − M
Reel of 250
Tube of 40
−55°C to 125°C
SOP − NS
Reel of 2000
Tube of 90
TSSOP − PW
Reel of 2000
Reel of 250
CD74HC191E
CD74HCT191E
CD74HC191M
CD74HC191M96
CD74HC191MT
CD74HCT191M
CD74HC190NSR
CD74HC190PW
CD74HC190PWR
CD74HC190PWT
CD54HC190F3A
CDIP − F
Tube of 25
CD54HC191F3A
CD54HCT191F3A
CD54HC190F3A
CD54HC191F3A
CD54HCT191F3A
HJ190
HCT191M
HC190M
HC191M
TOP-SIDE
MARKING
CD74HC190E
CD74HC191E
CD74HCT191E
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
description/ordering information (continued)
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes
high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading
(see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes
low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO
(see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to
the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
FUNCTION TABLE
INPUTS
LOAD
H
H
L
H
CTEN
L
L
X
H
D/U
L
H
X
X
X
X
CLK
FUNCTION
Count up
Count down
Asynchronous preset
No change
D/U or CTEN should be changed only when clock is high.
X = Don’t care
Low-to-high clock transition
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
