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Data Sheet
intersil.co
Te
t our
www.
c ont a c
SIL or
INTER
1-888-
®
CA3310, CA3310A
May 2001
File Number
3095.3
CMOS, 10-Bit, A/D Converters with
Internal Track and Hold
The Intersil CA3310 is a fast, low power, 10-bit successive
approximation analog-to-digital converter, with
microprocessor-compatible outputs. It uses only a single 3V
to 6V supply and typically draws just 3mA when operating at
5V. It can accept full rail-to-rail input signals, and features a
built-in track and hold. The track and hold will follow high
bandwidth input signals, as it has only a 100ns (typical) input
time constant.
The ten data outputs feature full high-speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. Separate 8 MSB and 2 LSB enables,
a data ready flag, and conversion start and ready reset
inputs complete the microprocessor interface.
An internal, adjustable clock is provided and is available as
an output. The clock may also be driven from an external
source.
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . . . 15mW
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3V to 6V
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13µs
• Built-In Track and Hold
• Rail-to-Rail Input Range
• Latched Three-state Output Drivers
• Microprocessor-Compatible Control Lines
• Internal or External Clock
Applications
• Fast, No-Droop, Sample and Hold
• Voice Grade Digital Audio
• DSP Modems
• Remote Low Power Data Acquisition Systems
•
µP
Controlled Systems
Part Number Information
PART
NUMBER
CA3310E
CA3310M
CA3310AM
LINEARITY
(INL, DNL)
±0.75
LSB
±0.75
LSB
±0.5
LSB
TEMP.
RANGE
(
o
C)
-40 to 85
-40 to 85
-40 to 85
PKG.
NO.
E24.6
M24.3
M24.3
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
Pinout
CA3310, CA3310A
(PDIP, SOIC)
TOP VIEW
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
DRDY
V
SS
(GND)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
V
IN
V
REF
+
R
EXT
CLK
STRT
V
REF
-
V
AA
+
V
AA
-
OEL
OEM
DRST
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
CA3310, CA3310A
Functional Block Diagram
STRT
V
DD
V
SS
V
IN
ALL
LOGIC
CONTROL
AND
TIMING
CLOCK
R
EXT
CLK
DRDY
Q
CLK
CLR
DRST
V
REF
+
16C
OEM
D9 (MSB)
50ÞΩ
SUBSTRATE
RESISTANCE
8C
D8
4C
D7
2C
V
AA
+
V
AA
-
D6
C
32
C
31
16C
10-BIT
SUCCESSIVE
APPROXIMATION
REGISTER
10-BIT
EDGE
TRIGGERED
“D”
LATCH
D5
D4
8C
D3
4C
D2
2C
D1
C
D0 (LSB)
C
OEL
V
REF
-
2
CA3310, CA3310A
Typical Application Schematics
+5V SUPPLY
4.7µF
TAN
8
3 100Ω
±10%
ICL7663S
1
6
ADJUST
GAIN
4
A
R2
A
R1
+
V
IN
-
R4
4
3
+
7
8
6
5
10K
1
D
ADJUST
OFFSET
R5
47pF
R3
100
0.1
+8V
TO
+15V
A
5
A
A
V
AA
-
DRDY
A
OPTIONAL
CLAMP
V
DD
V
IN
CLK
R
EXT
V
SS
UNLESS NOTED,
ALL RESISTORS =
1% METAL FILM,
POTS = 10 TURN, CERMET
D = DIGITAL GROUND
A = ANALOG GROUND
2MHz CLOCK
NC
DATA READY FLAG
4.5V
75V
5K
28.7K
4.7µF +
TAN
A
OEM
V
REF
-
OEL
CA3310/A
D0 - D9
V
REF
+
STRT
DRST
START CONVERSATION
RESET FLAG
HIGH BYTE ENABLE
LOW BYTE ENABLE
OUTPUT DATA
+
0.1µF CER
A
V
AA
+
V
DD
D
2 CA3140
-
0.1
-1V
TO
-15V
A
100
A
D
INPUT RANGE
0V To 2.5V
0V To 5V
0V To 10V
-2.5V To +2.5V
-5V To +5V
R1
4.99K
4.99K
10K
4.99K
10K
R2
9.09K
4.53K
4.53K
9.09K
9.09K
R3
OPEN
OPEN
OPEN
9.09K
9.09K
R4
4.99K
4.99K
10K
4.99K
10K
R5
9.09K
4.53K
4.53K
4.53K
4.53K
3
CA3310, CA3310A
Absolute Maximum Ratings
Digital Supply Voltage V
DD
. . . . . . . . . . . . . . V
SS
-0.5V to V
SS
+7V
Analog Supply Voltage (V
AA
+) . . . . . . . . . . . . . . . . . . . . V
DD
±0.5V
Any Other Terminal . . . . . . . . . . . . . . . . V
SS
-0.5V to V
DD
+ 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20mA
DC Output Drain Current, per Output . . . . . . . . . . . . . . . . . .
±35mA
Total DC Supply or Ground Current. . . . . . . . . . . . . . . . . . . .
±70mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature (T
STG
) . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
T
A
= 25×
o
C, V
DD
= V
AA
+ = 5V, V
REF
+ = 4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1MHz, Unless
Otherwise Specified
TEST CONDITIONS
MIN
10
CA3310
CA3310A
CA3310
CA3310A
CA3310
CA3310A
CA3310
CA3310A
-
-
-
-
-
-
-
-
In Series with Input Sample Capacitors
During Sample State
During Hold State
At V
IN
= V
REF
+ = 5V
At V
IN
= V
REF
- = 0V
STRT = V+, CLK = V+
At V
IN
= V
REF
+ = 5V
At V
IN
= V
REF
- = 0V
(Note 3)
(Note 3)
From Input RC Time Constant
Over V
DD
= 3V to 6V (Note 3)
Over V
DD
= 3V to 6V (Note 3)
Except CLK
(Note 3)
CLK Only (Note 3)
I
SOURCE
= -4mA
I
SINK
= 6mA
Except DRDY
Except DRDY (Note 3)
-
-
-
-
-
-
-
V
REF
- +1
V
SS
-0.3
-
70
-
-
-
-
4.6
-
-
-
TYP
-
±0.5
±0.25
±0.5
±0.25
±0.25
-
±0.25
-
330
300
20
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-
-
-
MAX
-
±0.75
±0.5
±0.75
±0.5
±0.5
±0.25
±0.5
±0.25
-
-
-
+300
-100
1
-1
V
DD
+0.3
V
REF
+ -1
-
-
30
±1
10
±400
-
0.4
±1
20
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Ω
pF
pF
µA
µA
µA
µA
V
V
MHz
% of V
DD
% of V
DD
µA
pF
µA
V
V
µA
pF
ACCURACY
(See Text For Definitions)
Resolution
Differential Linearity Error
Integral Linearity Error
Gain Error
Offset Error
ANALOG INPUT
Input Resistance
Input Capacitance
Input Capacitance
Input Current
Static Input Current
Input + Full-Scale Range
Input - Full-Scale Range
Input Bandwidth
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
Input Current
DIGITAL OUTPUTS
D0 - D9, DRDY
High-Level Output Voltage
Low-Level Output Voltage
Three-State Leakage
Output Capacitance
DIGITAL INPUTS
DRST, OEL, OEM, STRT, CLK
4
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