74AC11 — Triple 3-Input AND Gate
January 2008
74AC11
Triple 3-Input AND Gate
Features
■
I
CC
reduced by 50%
■
Outputs source/sink 24mA
General Description
The AC11 contains three, 3-input AND gates.
Ordering Information
Order
Number
74AC11SC
74AC11SJ
74AC11MTC
74AC11PC
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
, C
n
O
n
Description
Inputs
Outputs
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com
74AC11 — Triple 3-Input AND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
2.0V to 6.0V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com
2
74AC11 — Triple 3-Input AND Gate
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
T
A
=
+25°C
Conditions
V
OUT
=
0.1V
or V
CC
– 0.1V
V
OUT
=
0.1V
or V
CC
– 0.1V
I
OUT
=
–50µA
T
A
=
–40°C to +85°C
Guaranteed Limits
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
µA
mA
mA
µA
V
V
V
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
I
OUT
=
50µA
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
I
IN(3)
I
OLD
I
OHD
I
CC(3)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
2.0
20.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com
3
74AC11 — Triple 3-Input AND Gate
AC Electrical Characteristics
T
A
=
+25°C,
C
L
=
50pF
Symbol
t
PLH
t
PHL
T
A
=
–40°C to +85°C,
C
L
=
50pF
Min.
1.0
1.0
1.0
1.0
Parameter
Propagation Delay
Propagation Delay
V
CC
(V)
(4)
3.3
5.0
3.3
5.0
Min.
1.5
1.5
1.5
1.5
Typ.
5.5
4.0
5.5
4.0
Max.
9.5
8.0
8.5
7.0
Max.
10.0
8.5
9.5
7.5
Units
ns
ns
Note:
4. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
OPEN
V
CC
=
5.0V
Typ.
4.5
20.0
Units
pF
pF
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com
4
74AC11 — Triple 3-Input AND Gate
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
0.25
0.10
C
0.10 C
SEE DETAIL A
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com
5
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