SO
8
PHC21025
Complementary intermediate level FET
Rev. 04 — 17 March 2011
Product data sheet
1. Product profile
1.1 General description
Intermediate level N-channel and P-channel complementary pair enhancement mode
Field-Effect Transistor (FET) in a plastic package using vertical D-MOS technology. This
product is designed and qualified for use in computing, communications, consumer and
industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
Motor and actuator drivers
Power management
Synchronized rectification
1.4 Quick reference data
Table 1.
Symbol
V
DS
Quick reference data
Parameter
drain-source voltage
Conditions
T
j
≥
25 °C; T
j
≤
150 °C;
N-channel
T
j
≥
25 °C; T
j
≤
150 °C;
P-channel
I
D
P
tot
R
DSon
drain current
total power dissipation
drain-source on-state
resistance
T
sp
≤
80 °C; P-channel
T
sp
≤
80 °C; N-channel
T
amb
= 25 °C
V
GS
= -10 V; I
D
= -1 A;
T
j
= 25 °C; P-channel;
see
Figure 16;
see
Figure 19
V
GS
= 10 V; I
D
= 2.2 A;
T
j
= 25 °C; N-channel;
see
Figure 15;
see
Figure 18
[1]
Min
-
-
-
-
-
-
Typ
-
-
-
-
-
Max Unit
30
-30
-2.3
3.5
1
V
V
A
A
W
Static characteristics
0.22 0.25
Ω
-
0.08 0.1
Ω
NXP Semiconductors
PHC21025
Complementary intermediate level FET
Quick reference data
…continued
Parameter
gate-drain charge
Conditions
V
GS
= -10 V; I
D
= -2.3 A;
V
DS
= -15 V; T
j
= 25 °C;
P-channel; see
Figure 12
V
GS
= 10 V; I
D
= 2.3 A;
V
DS
= 15 V; T
j
= 25 °C;
N-channel; see
Figure 11
Min
-
Typ
3
Max Unit
-
nC
Table 1.
Symbol
Q
GD
Dynamic characteristics
-
2.5
-
nC
[1]
Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a
thermal resistance from ambient to solder point of 90 K/W.
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
4
S1
G1
S2
G2
8
5
D1
D1
D2
D2
Simplified outline
Graphic symbol
SOT96-1 (SO8)
sym114
3. Ordering information
Table 3.
Ordering information
Package
Name
PHC21025
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
PHC21025
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 17 March 2011
2 of 16
NXP Semiconductors
PHC21025
Complementary intermediate level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
GS
V
GSO
I
D
I
DM
Limiting values
Parameter
drain-source voltage
gate-source voltage
gate-source voltage
drain current
peak drain current
open drain
T
sp
≤
80 °C; P-channel
T
sp
≤
80 °C; N-channel
T
sp
= 25 °C; pulsed; N-channel;
see
Figure 2
T
sp
= 25 °C; pulsed; P-channel;
see
Figure 3
P
tot
total power dissipation
T
amb
= 25 °C
T
sp
= 80 °C; see
Figure 1
T
amb
= 25 °C
T
stg
T
j
I
S
I
SM
storage temperature
junction temperature
source current
peak source current
T
sp
≤
80 °C; P-channel
T
sp
≤
80 °C; N-channel
T
sp
= 25 °C; pulsed; P-channel
T
sp
= 25 °C; pulsed; N-channel
[1]
[2]
[3]
[4]
[5]
[6]
Pulse width and duty cycle limited by maximum junction temperature.
Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a thermal resistance from ambient to
solder point of 90 K/W.
Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with thermal resistance
from ambient to solder point of 90 K/W.
Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a Thermal resistance from ambient
to solder point of 27.5 K/W.
Pulse width and duty cycle limited by maximum junction temperature.
[6]
[6]
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
150 °C; N-channel
T
j
≥
25 °C; T
j
≤
150 °C; P-channel
Min
-
-
-
-20
-
-
-
-
-
-
-
-
-65
-
-
-
-
-
Max
30
-30
-
20
-2.3
3.5
14
-10
1
2
1.3
2
150
150
-1.25
1.5
-5
6
Unit
V
V
V
V
A
A
A
A
W
W
W
W
°C
°C
A
A
A
A
[1]
[2]
[3]
[4]
[5]
Source-drain diode
PHC21025
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 17 March 2011
3 of 16
NXP Semiconductors
PHC21025
Complementary intermediate level FET
2.5
P
tot
(W)
2.0
mlb836
10
2
I
D
(A)
10
(1)
mlb833
t
p
=
10μs
1.5
1
1.0
P
δ
=
t
p
T
1 ms
0.5
10
−1
t
p
t
T
DC
0.1 s
0
0
50
100
150
T
s
(°C)
200
10
−2
10
−1
1
10
V
DS
(V)
10
2
δ
= 0.01.
T
s
= 80 °C.
(1) R
DSon
limitation.
Fig 1.
Power derating curve
−10
2
I
D
(A)
−10
(1)
Fig 2.
SOAR; N-channel
mbe155
t
p
=
10
μs
−1
t
p
T
1 ms
P
δ
=
−10
−1
t
p
DC
0.1 s
t
T
−10
−2 −1
−10
−1
−10
V
DS
(V)
−10
2
δ
= 0.01
T
s
= 80 °C.
(1) R
DSon
limitation.
Fig 3.
SOAR; P-channel
PHC21025
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 17 March 2011
4 of 16
NXP Semiconductors
PHC21025
Complementary intermediate level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance from junction to solder
point
Conditions
Min
-
Typ
-
Max
35
Unit
K/W
10
2
R
th j-s
(K/W)
10
mbe152
δ
=
0.75
0.5
0.33
0.2
0.1
0.05
t
p
T
1
0.02
0.01
0
P
δ
=
t
p
T
t
10
−1
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PHC21025
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 17 March 2011
5 of 16
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