Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
FEATURES
•
Wide supply voltage range from 1.2 V to 3.6 V
•
Complies with JEDEC standard JESD8-B/JESD36
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Synchronous reset
•
Synchronous counting and loading
•
Two count enable inputs for n-bit cascading
•
Positive edge-triggered clock.
•
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
DESCRIPTION
The 74LVC163 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC163 is a synchronous presettable binary
counter which features an internal look-head carry and can
be used for high-speed counting. Synchronous operation
is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (pin CP). The
outputs (pins Q0 to Q3) of the counters may be preset to a
74LVC163
HIGH-level or LOW-level. A LOW-level at the parallel
enable input (pin PE) disables the counting action and
causes the data at the data inputs (pins D0 to D3) to be
loaded into the counter on the positive-going edge of the
clock (provided that the set-up and hold time requirements
for PE are met). Preset takes place regardless of the levels
at count enable inputs (pins CEP and CET). A LOW-level
at the master reset input (pin MR) sets all four outputs of
the flip-flops (pins Q0 to Q3) to LOW-level after the next
positive-going transition on the clock input (pin CP)
(provided that the set-up and hold time requirements for
PE are met). This action occurs regardless of the levels at
input pins PE, CET and CEP. This synchronous reset
feature enables the designer to modify the maximum count
with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (pins CEP and CET)
must be HIGH to count. The CET input is fed forward to
enable the terminal count output (pin TC). The TC output
thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH-level output of Q0.
This pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by t
PHL
(propagation delay CP to TC) and t
su
(set-up time CEP to CP) according to the
1
formula: f
max
=
------------------------------------ .
-
t
PHL
(
max
)
+
t
su
2004 May 05
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
CP to Qn
CP to TC
CET to TC
f
clk(max)
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
TYPE NUMBER
74LVC163D
74LVC163DB
74LVC163PW
74LVC163BQ
TEMPERATURE
RANGE
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
PINS
16
16
16
16
PACKAGE
SO16
SSOP16
TSSOP16
DHVQFN16
maximum clock frequency
input capacitance
power dissipation capacitance per gate
notes 1 and 2
PARAMETER
propagation delay:
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
4.0
4.6
3.5
200
5.0
17
74LVC163
TYPICAL
ns
ns
ns
UNIT
MHz
pF
pF
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT109-1
SOT338-1
SOT403-1
SOT763-1
2004 May 05
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset
FUNCTION TABLE
See note 1.
OPERATING
MODES
Reset (clear)
Parallel load
Count
Hold
(do nothing)
Note
1. * = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level.
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
INPUT
MR
l
h
h
h
h
h
CP
↑
↑
↑
↑
X
X
CEP
X
X
X
h
l
X
CET
X
X
X
h
X
l
PE
X
l
l
h
h
h
Dn
X
l
h
X
X
X
74LVC163
OUTPUT
Qn
L
L
H
count
q
n
q
n
TC
L
L
*
*
*
L
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock
transition.
X = don’t care.
↑ =
LOW-to-HIGH clock transition.
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MR
CP
D0
D1
D2
D3
CEP
GND
PE
CET
Q3
Q2
Q1
Q0
TC
V
CC
SYMBOL
DESCRIPTION
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
data input
data input
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
flip-flop output
flip-flop output
flip-flop output
terminal count output
supply voltage
2004 May 05
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模拟与混合信号
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