CD4013B Types
COS/MOS
Dual
Features:
•
•
Set-Reset capability
Static flip-flop operation - retains state
indefinitely with clock level either
"high" or "low"
Medium-speed operation - 16 MHz (typ.)
clock toggle rate at 10V
VDD
'0'
-Type Flip-Flop
High-Voltage Types (20-Volt Rating)
•
The RCA-CD40138 consists of two identical,
independent data-type flip-flops. Each flip-
flop has independent data,' set, reset, and
clock inputs and
Q
and
0
outputs. These de-
vices can
be
used for shift register applica-
tions, and, by connecting
Q
output to the
data Input, for counter and toggle applica-
tions. The logic level present at the
0
input
IS transferred to the
Q
output during the
positive-going transition of the clock pulse.
Setting or resetting IS independent of the
clock and IS accomplished by a high level on
the set or reset line, respectively.
The CD4013B types are supplied
In
14-lead
hermetic dual-In-line ceramic packages
(0
and F suffixes), 14-lead dual-in-Ilne plastic
packages (E SUffiX), 14-lead ceramic flat
packages (K suffiX), and In chip form (H
suffiX)
• Standardized symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 J.1A at 18 V
over full package temperature range;
100 nA at 18 V and 25
0
C
• Noise margin (over full package
temperature range):
1 Vat VDD=5 V
2 V at VDD=10 V
2.5 Vat VDD=15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CD4013B
FUNCTIONAL DIAGRAM
Applications:
•
Registers, counters, control circuits
RECOMMENDED OPERATING CONDITIONS
At TA
=
25" C,
Except as Noted. For maximum reliability, nominal operating condi-
Fig.
1 -
Typical output low (sink
J
current characteristics.
tions should be selected so that operation is always within the following ranges:
CHARACTERISTIC
Supply·Voltage Range
(For T A
=
Fu" Package
Temperature Rangel
V DD
(V)
MIN.
MAX.
18
V
LIMITS
UNITS
'B"
t
~:
I~
-
5
3
40
20
15
140
60
40
II.
,
DRAIN-TO-SOURCE VOLTAGE
I~
vc
-
Data Setup Time ts
10
15
5
-
-
ns
-
-
ns
(Vos)-v
'Ut\Z"'J'''-'
Clock Pulse Width tw
10
15
5
Fig.
2 -
Mmlmum output low (smk)
current charactenstics.
-
35
DR'IN- TO-SOURCE VOlT'GE (VDSI-V
Clock Input Frequency
fCl
10
15
5
dc
8
12
MHz
1·..
·IEN'
-': .wn,
OlT.G
1-'
Clock Rise or Fa" Time
trCL,~
tfCL
10
15
5
-
-
-
180
80
50
15
4
1
jJ.S
:
I
-
-
ns
Set or Reset Pulse Width
tw
10
15
-
"If more than one unit IS cascaded In a parallel clocked operation, trCL should be made less than or equal to
the sum of the fixed propagation delay time at 15 pF and the transition time of the output drtvlng stage for
the estimated capacitive load.
~
.lllil
Fig.
3 -
Typical output
high"(~~~~~~i'
current characteristics.
!
82 _________________________________________________________________________
CD4013B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -56, +25, +125 Apply to 0, F, H Pkgs.
Values at -40,+25,+85 Apply to E Pkgs_
UNITS
+25
-55 -40 +85
+125 Min.
Typ.
Max.
1
2
4
20
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
1
2
4
20
30
60
120
600
30
60
120
600
DRAIN-TO-SOURCE VOLTAGE fVDSI-V
CHARAC-
TERISTIC
CONDITIONS
Vo
VIN VDD
(V)
(V)
(V)
QUiescent
Device
Current
'00 Max
Output L.ow
(Sink)
Current,
'OL Min.
Output High
(Source)
Current,
IOH Min
Output Volt·
age:
Low-Level.
VOL Max.
Output Volt·
age:
H,gh·Level,
VO H Min.
Input Low
Voltage,
V,L Max.
Input High
Voltage,
V,H Min.
Input
Current,
"N Max.
-
-
-
-
0,5
0,10
0,15
0,20
0,5
0,10
0,15
0,5
0,5
0,10
0,15
0,5
0,10
0,15
0,5
0,10
0,15
5
10
15
20
5
10
15
5
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
-
-
-
-
0.02
0.02
0.02
004
1
2.6
6.8
-1
-3.2
-2.6
-6.8
0
0
0
5
10
15
1
2
4
20
pA
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0.61
0.42 0.36 0.51
1.5
0.9
1.1
1.3
4
2.8
2.4
3.4
-0.61 -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6
-1.5 -1.1 -0.9 -1.3
-4
-2.8 -2.4 -3.4
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3
4
3.5
7
-
-
-
Fig.
4 -
Minimum output high (source)
current characteristIcs.
-
-
-
-
0.05
0.05
0.05
rnA
-
-
-
-
-
-
-
-
4.95
9.95
14.95
V
-
-
-
1.5
3
4
Fig.
5 -
LOAD CAPACITANCE (C L I-p"
-
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
15,13.5
-
-
-
-
-
-
0,18
-
-
-
-
3.5
7
-
-
TypIcal propagatIon delay tIme vs. load
capacItance (CLOCK or SET
to
O,CLDCK
or RESET
to
lJJ.
11
±0.1
±0.1
±1
±1
11
-
-
-
-
-
V
-
-
±10-5 ±0.1
pA
../
'
../
'
'- x
,
,
o
ij
_0
CHAMGE
LOAD CAPACITANCE CCl)-pF
,',
I
,',
Fig.
6 -
TYPIcal propagatIon delay tIme vs. load
capacItance (SET
to
Q
or RESET
to
O.
LOGIC O' LOW
LOGIC I' HIGH
•
&
LEVEL CHANGE
X' DON'T CARE
H(N)'
FFl/Ff2 TERWINAL
ASSIGNMENTS
*6f
811O---~
SET
1(131
2(121
*
PROTECTED ARE
ALL INPUTS
By
COS'MOS PROTECTION
NETWORK
i!;
DD
VSS
Fig.
7 -
Logic diagram and truth table for CD40138
(one of
two
Identical flip· flops).
.
SUPPLY vOLTAGE
(VDr..~-V
92CS·2~392A2
Fig.
8 -
TYPIcal maxImum clock frequency
supply voltage.
lIS.
________________________________________________________________________ 83
•
CD4013B Types
MAXIMUM RATINGS,
Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DO)
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PO).
For T A'" -40 to +60 o C (PACKAGE TYPE E)
. . . . . . . ..
500 mW
For T A'" +60 to +85
0
C (PACKAGE TYPE E)
.
Derate Linearly at 12 mW/oC to 200 mW
. . . . . . . ..
For TA ;: -55 to +100
0
C (PACKAGE TYPES 0, F)
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A;: +100 to +125
0
C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A
=
FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
-55 to +125
0
C
PACKAGE TYPES 0, F, H . . . . .
PACKAGE TYPE E .
-40 to +85
0
C
STORAGE TEMPERATURE RANGE (T stg )
-65 to +150
0
C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
AMBIENT TEMPERATURE (TAI·2S:C
10'
10'
10'
106
INPUT FREQUENCY (I,I-H.
Fig.
9 -
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA
Typical power dissipation
vs. frequency,
=
2!tC; Input t r ,
t,=
20ns, CL
=
50pF, RL
=
200
kr2
TEST
CONDITIONS
r---
TEST CIRCUITS
LIMITS
UNITS
MIN.
TYP.
MAX.
Vss
o
INPUTS
CHARACTERISTIC
V DD
(V)
Propagation Delay Time:
Clock to
Q
or
Q
Outputs
t pHL • tpLH
5
10
15
5
10
15
5
-
-
-
-
150
65
45
150
65
45
200
85
60
100
50
40
7
16
24
70
30
20
90
40
25
20
10
7
300
130
90
300
VSS
ns
00
Set to
Q
or Reset to
Q
tp LH
-
-
-
-
-
-
130
90
400
170
120
200
100
80
ns
tzCS-114QIAI
Fig. 10
-
Quiescent device current.
-
Set to
Q
or Reset to
Q
tpHL
10
15
5
ns
Transition Time t THL • tTLH
10
15
5
-
-
3.5
8
12
-
-
ns
Maximum Clock Input Frequency
Frequency
#
tCL
10
15
5
10
15
5
-
-
:~MO'~
"";
Vss
NOTE.
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Voo ORVSS
MHz
-
140
60
40
180
80
50
40
20
15
15
4
1
J.l.s
ns
ns
ns
Mmimum Clock Pulse Width
tw
Fig.
11 -
Input vo/rage.
Minimum Set or Reset Pulse
Width
tw
10
15
5
10
15
5
Minimum Data Setup Time ts
-
-
-
-
-
-
-
-
1 N P U
Voo
s
O
Voo
NOT[
M[ASUR[ INPUTS
S[QU[NTIALLY.
TO 80TH
Voo AND Vss
CONH[CT ALL
UNUSED
INPUTS TO
[ITH[II
Voo 011
VSS
VSS
~_
o
~
Vss
Clock Input Rise or Fall Time
t rCL , ttCL
Input Capacitance CIN
#Input t r , tf '" 5 ns.
-
-
-
5
10
15
Any Input
-
-
-
Fig.
12 -
Input current.
75
pF
84 ________________________________________________________________________
CD4013B Types
01
I.
I.
Voo
iii
CLOCK
I
RESET I
2
3
13
12
10
9
02
Q2
CLOCK 2
RESET 2
01
SET!
02
SET 2
vss
TOP VIEW
8
TERMINAL ASSIGNMENT
DIMENSIONS AND PAD LAYOUT FOR CD4013BH
55-63
1 397-1600)
54-62
(1.372-1.574)
92CM- 30975
Dimensions In parentheses are In mlfl,meters and are
derived (rom the basIc Inch dimensions as indicated.
3 Inch).
Grid graduations are In mils
"0-
The phorographsanddllllllllslOm of cdch
COS/MaS
chip represent a chip when II
"
p."t of rill] w.lfer
When the
w~fer
IS cut IIlto chips. the cle.JVage
o
angles are
57
IIlstead of 90 with respect to the
face of the chip Therefore. the Isoldted chip IS
actually
7
mils
(0
17
mm) larger
III
both dllnemlOlls
____________________________________________________________________ 85
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