CYRF7936
2.4-GHz CyFi™ Transceiver
Features
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Operating voltage from 1.8 V to 3.6 V
Operating temperature from 0 °C to 70 °C
Space saving 40-pin QFN 6 × 6 mm package
2.4-GHz direct sequence spread spectrum (DSSS) radio
transceiver
Operates in the unlicensed worldwide industrial, scientific, and
medical (ISM) band (2.400 GHz to 2.483 GHz)
21-mA operating current (transmit at –5 dBm)
Transmit power up to +4 dBm
Receive sensitivity up to –97 dBm
Sleep current less than 1 µA
DSSS data rates up to 250 kbps, Gaussian frequency-shift
keying (GFSK) data rate of 1 Mbps
Low external component count
Auto transaction sequencer (ATS) - no MCU intervention
Framing, length, CRC16, and auto acknowledge (ACK)
Power management unit (PMU) for MCU
Fast startup and fast channel changes
Separate 16 byte transmit and receive FIFOs
Dynamic data rate reception
Receive signal strength indication (RSSI)
Serial peripheral interface (SPI) control while in sleep mode
4-MHz SPI microcontroller interface
Battery voltage monitoring circuitry
Supports coin-cell operated applications
Applications
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Wireless sensor networks
Wireless actuator control
Home automation
White goods
Commercial building automation
Automatic meter readers
Precision agriculture
Remote controls
Consumer electronics
Personal health and fitness
Toys
Applications Support
The CYRF7936 CyFi™ transceiver is a radio IC designed for low
power embedded wireless applications. It can be used only with
Cypress’s PSoC programmable system-on-chip. Combined with
the PSoC and a CyFi network protocol stack, CYRF7936 can be
used to implement a complete CyFi wireless system.
See
www.cypress.com
for development tools, reference
designs, and application notes.
Logic Block Diagram
V
REG
L/D
V
BAT
V
IO
IRQ
SS#
SCK
MISO
MOSI
V
DD
V
CC
PACTL
PMU
CyFi Radio Modem
Data
Interface
and
Sequencer
GFSK
Modulator
DSSS
Baseband
& Framer
GFSK
Demodulator
RF
P
RF
N
RF
BIAS
SPI
RSSI
Xtal Osc
Synthesizer
RST
XTAL XOUT
GND
Cypress Semiconductor Corporation
Document #: 001-48013 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 8, 2012
CYRF7936
Contents
Pinouts .............................................................................. 3
Functional Overview ........................................................ 4
Data Transmission Modes ........................................... 4
Packet Framing ........................................................... 4
Packet Buffers ............................................................. 5
Auto Transaction Sequencer (ATS) ............................ 5
Data Rates .................................................................. 5
Functional Block Overview .............................................. 6
2.4-GHz CyFi Radio Modem ....................................... 6
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and Radio Configuration Registers ..... 6
SPI Interface ................................................................ 6
Interrupts ..................................................................... 8
Clocks .......................................................................... 8
Power Management .................................................... 8
Receiver Front End ..................................................... 8
Receive Spurious Response ....................................... 9
Application Examples ...................................................... 9
Absolute Maximum Ratings .......................................... 13
Operating Conditions ..................................................... 13
DC Characteristics ......................................................... 13
AC Characteristics ......................................................... 14
RF Characteristics .......................................................... 15
Typical Operating Characteristics ................................ 17
Ordering Information ...................................................... 19
Ordering Code Definition ........................................... 19
Package Description ...................................................... 20
Document Conventions ................................................. 21
Acronyms .................................................................. 21
Units of Measure. ...................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC Solutions ......................................................... 23
Document #: 001-48013 Rev. *G
Page 2 of 23
CYRF7936
Pinouts
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
V
BAT0
38
V
REG
40
RST 34
Corner
tabs
V
DD
35
L/D 37
NC 39
NC 36
NC 31
NC 32
V
IO
33
XTAL 1
NC
V
CC
NC
NC
V
BAT1
V
CC
V
BAT2
NC
2
3
4
5
6
7
8
9
* E- PAD Bottom Side
30
29
28
PACTL / GPIO
XOUT / GPIO
MISO / GPIO
MOSI / SDAT
IRQ / GPIO
CYRF7936
CyFi Transciever
40 lead QFN
27
26
25 SCK
24 SS
23 NC
22 NC
21 NC
RF
BIAS
10
11 RF
P
12 GND
13 RF
N
14 NC
15 NC
16 V
CC
17 NC
18 NC
19 RESV
20 NC
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
1
Name
XTAL
Type
I
NC
Default
I
12-MHz crystal
Connect to GND
Description
2, 4, 5, 9, 14, 15, NC
17, 18, 20, 21, 22,
23, 31, 32, 36, 39
3, 7, 16
6, 8, 38
10
11
12
13
19
24
25
26
27
28
29
30
33
34
V
CC
V
BAT(0-2)
RF
BIAS
RF
P
GND
RF
N
RESV
SS#
SCK
IRQ
MOSI
MISO
XOUT
PACTL
V
IO
RST
Pwr
Pwr
O
I/O
GND
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
Pwr
I
I
I
I
O
I
Z
O
O
I
O
I
V
CC
= 2.4 V to 3.6 V. Typically connected to V
REG
.
V
BAT
= 1.8 V to 3.6 V. Main supply.
RF I/O 1.8 V reference voltage
Differential RF signal to and from antenna
Ground
Differential RF signal to and from antenna
Must be connected to GND
SPI enable, active LOW assertion. Enables and frames transfers.
SPI clock
Interrupt output (configurable active HIGH or LOW), or GPIO
SPI data input pin master out slave in (MOSI) or serial data (SDAT)
SPI data output pin - master in slave out (MISO), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN = 0 and SS# is deasserted.
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (configure as GPIO drive LOW).
Control signal for external PA, T/R switch, or GPIO
I/O interface voltage, 1.8 V to 3.6 V
Device reset. Internal 10-k pull-down resistor. Active HIGH, typically connect
through a 0.47-F capacitor to V
BAT.
Must have RST = 1 event the first time power
is applied to the radio. Otherwise, the radio control register state is unknown.
Decoupling pin for 1.8 V logic regulator, connect through a 0.47-F capacitor to
GND.
Page 3 of 23
35
V
DD
Pwr
Document #: 001-48013 Rev. *G
CYRF7936
Table 1. Pin Description - CYRF7936 40-Pin QFN
(continued)
Pin Number
37
40
E-pad
Corner tabs
Name
LVD
V
REG
GND
NC
Type
O
Pwr
GND
NC
Default
Description
PMU inductor or diode connection, when used. If not used, connect to GND.
PMU boosted output voltage feedback
Must be soldered to ground
Do not solder the tabs and keep other signal traces clear. All tabs are common to
the lead frame or paddle, which is grounded after the pad is grounded. While they
are visible to the user, they do not extend to the bottom.
Functional Overview
The CYRF7936 IC is designed to implement wireless device
links operating in the worldwide 2.4-GHz ISM frequency band. It
is intended for systems compliant with worldwide regulations
covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1
V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry
Canada), and TELEC ARIB_T66_March, 2003 (Japan).
The CYRF7936 contains a 2.4-GHz CyFi radio modem, which
features a 1-Mbps GFSK radio front-end, packet data buffering,
packet framer, DSSS baseband controller, and RSSI.
CYRF7936 features a SPI interface for data transfer and device
configuration.
The CyFi radio modem supports 98 discrete 1-MHz channels
(regulations may limit the use of some of these channels in
certain jurisdictions).
The baseband performs DSSS spreading and despreading,
start-of-packet (SOP), end-of-packet (EOP) detection, and
CRC16 generation and checking. The baseband may also be
configured to automatically transmit ACK handshake packets
whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
In addition, the CYRF7936 IC has a power management unit
(PMU), which allows direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device, and may supply external devices.
Packet Framing
The CYRF7936 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SOP marker. The
SOP_CODE_ADR PN code used for the SOP is different from
that used for the “body” of the packet, and if necessary may be
a different length. SOP must be configured to be the same length
on both sides of the link.
Length
This is the first eight bits after the SOP symbol and is transmitted
at the payload data rate. An EOP condition is inferred after
reception of the number of bytes defined in the length field, plus
two bytes for the CRC16.
CRC16
The device may be configured to append a 16-bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed. The
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
CRC16 detects the following errors:
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Any one bit in error.
Any two bits in error (irrespective of how far apart, which
column, and so on).
Any odd number of bits in error (irrespective of the location).
An error burst as wide as the checksum itself.
Data Transmission Modes
The CyFi radio transceiver supports two different data
transmission modes:
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Figure 2
shows an example packet with SOP, CRC16, and
lengths fields enabled and
Figure 3
shows a standard ACK
packet.
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In 8DR mode, DSSS is enabled and eight bits are encoded in
each derived code symbol transmitted.
Both 64 chip and 32 chip pseudo noise (PN) codes are supported
in 8DR mode. In general, lower data rates reduce packet error
rate in any given environment.
Document #: 001-48013 Rev. *G
Page 4 of 23
CYRF7936
Figure 2. Example Packet Format
P re a m b le
n x 16us
2 n d F ra m in g
S y m b o l*
P
SOP 1
1 s t F ra m in g
S y m b o l*
SOP 2
L e n g th
Packet
le n g th
1 B y te
P e rio d
P a y lo a d D a ta
C R C 16
*N o te :3 2 o r 6 4 u s
Figure 3. Example ACK Packet Format
P r e a m b le
n x 16us
2 n d F r a m in g
S y m b o l*
P
SO P 1
1 s t F r a m in g
S y m b o l*
SO P 2
C RC 16
C R C fie ld fr o m
r e c e iv e d p a c k e t.
2 B y te p e r io d s
*N o te :3 2 o r 6 4 u s
Packet Buffers
All data transmission and reception use the 16-byte packet
buffers: one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to
16 bytes of payload data in one burst SPI transaction. This is
then transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
Maximum packet length depends on the accuracy of the clock on
each end of the link. Packet lengths up to 40 bytes are supported
when the delta between the transmitter and receiver crystals is
60 ppm or better. Interrupts are provided to allow an MCU to use
the transmit and receive buffers as FIFOs. When transmitting a
packet longer than 16 bytes, the MCU can load 16 bytes initially,
and add further bytes to the transmit buffer as transmission of
data creates space in the buffer. Similarly, when receiving
packets longer than 16 bytes, the MCU must fetch received data
from the FIFO periodically during packet reception to prevent it
from overflowing.
Similarly, when receiving in transaction mode, the device
automatically:
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Waits in receive mode for a valid packet to be received
Transitions to transmit mode, transmits an ACK packet
Transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF7936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
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Auto Transaction Sequencer (ATS)
The CYRF7936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
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1000 kbps (GFSK)
250 kbps (32 chip 8DR)
125 kbps (64 chip 8DR)
Starts the crystal and synthesizer
Enters transmit mode
Transmits the packet in the transmit buffer
Transitions to receive mode and waits for an ACK packet
Transitions to the transaction end state when an ACK packet
is received or a timeout period expires
Document #: 001-48013 Rev. *G
Page 5 of 23
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