FAST CMOS 16-BIT BUS
IDT54/74FCT16652T/AT/CT/ET
IDT54/74FCT162652T/AT/CT/ET
TRANSCEIVER/
REGISTERS
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
–
Typical t
SK
(o) (Output Skew) < 250ps
– Low input and output leakage
≤1µA
(max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– V
CC
= 5V
±10%
• Features for FCT16652T/AT/CT/ET:
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25°C
• Features for FCT162652T/AT/CT/ET:
– Balanced Output Drivers:
±24mA
(commercial),
±16mA
(military)
– Reduced system switching noise
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25°C
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET
16-bit registered transceivers are built using advanced dual
metal CMOS technology. These high-speed, low-power de-
vices are organized as two independent 8-bit bus transceivers
with 3-state D-type registers. For example, the xOEAB and
x
OEBA
signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT16652T/AT/CT/ET are ideally suited for driving
high capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162652T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162652T/AT/CT/ET are plug-in replacements for the
FCT16652T/AT/CT/ET and ABT16652 for on-board bus inter-
face applications.
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
1
OEBA
1
CLKBA
1
SBA
1
CLKAB
1
SAB
B REG
2
OEAB
2
OEBA
2
CLKBA
2
SBA
2
CLKAB
2
SAB
B REG
D
C
1
A
1
A REG
1
B
1
D
C
2
A
1
A REG
2
B
1
D
C
D
C
TO 7 OTHER CHANNELS
2549 drw 01
TO 7 OTHER CHANNELS
2549 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2549/8
1
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
OEAB
1
CLKAB
1
SAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1 43
SO56-2
SO56-3 42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
SBA
1
OEAB
1
CLKAB
1
SAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2549 drw 04
1
OEBA
1
CLKBA
1
SBA
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
GND
2
SAB
2
CLKAB
GND
2
SBA
2
CLKBA
2
OEBA
GND
2
SAB
2
CLKAB
GND
2
SBA
2
CLKBA
2
OEBA
2OEAB
2OEAB
SSOP/
TSSOP/TVSOP
TOP VIEW
2549 drw 03
CERPACK
TOP VIEW
2
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Description
Data Register A Inputs
Data Register B Outputs
xBx
Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA
xOEAB, x
OEBA
Output Data Source Select Inputs
Output Enable Inputs
2549 tbl 01
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max. Unit
6.0
pF
8.0
pF
2549 lnk 02
Pin Names
xAx
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
xOEAB
L
L
X
H
L
L
L
L
H
H
H
x
OEBA
H
H
H
H
X
L
L
L
H
H
L
(2)
Inputs
Data I/O
(1)
xSAB
X
X
X
X
(2)
X
X
X
X
L
H
H
xSBA
X
X
X
X
X
X
(2)
L
H
X
X
H
xAx
Input
Input
Input
Unspecified
(1)
Output
Output
Input
Output
xBx
Input
Operation or Function
Isolation
Store A and B Data
xCLKAB xCLKBA
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
Unspecified
(1)
Store A, Hold B
Output
Store A in Both Registers
Input
Input
Input
Output
Output
Hold A, Store B
Store B in both Registers
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
2549 tbl 03
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or x
OEBA
inputs.
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clocks inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
L = LOW Voltage Level
ABSOLUTE MAXIMUM RATINGS
(1)
X = Don't care
Symbol
Description
Max.
↑
= LOW-to-HIGH Transition
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
V
TERM(3)
Terminal Voltage with Respect to
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
°C
mA
2549 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
3
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
2549 drw 05
2549 drw 06
x
OEAB
x
OEBA
x
CLKAB
x
CLKBA
x
SAB
x
SBA
x
OEAB
x
OEBA
x
CLKAB
x
CLKBA
x
SAB
x
SBA
L
L
X
X
X
L
H
H
X
X
L
X
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
BUS
A
BUS
B
BUS
A
BUS
B
2549 drw 07
2549 drw 08
x
OEAB
x
OEBA
x
CLKAB
x
CLKBA
x
SAB
x
SBA
x
OEAB
x
OEBA
x
CLKAB
x
CLKBA
x
SAB
x
SBA
X
L
L
H
X
H
↑
X
↑
X
↑
↑
X
X
X
X
X
X
H
L
H or L
H or L
H
H
STORAGE FROM
A AND/OR B
TRANSFER STORED
DATA TO A AND/OR B
4
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±10%;
Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
–
1.2
–
225
—
µA
V
mA
mV
µA
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
2549 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16652T
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
≤
4.5V
Min.
–50
2.5
2.4
2.0
—
—
Typ.
(2)
—
Max.
–
180
—
—
—
0.55
±1
Unit
mA
V
V
V
V
µA
2549 lnk 06
3.5
3.5
3.0
0.2
—
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
OUTPUT DRIVE CHARACTERISTICS FOR FCT162652T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
2549 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
5
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
