74HC40103
8-bit synchronous binary down counter
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the
40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC
standard no. 7A.
The 74HC40103 consists of an 8-bit synchronous down counter with a single output which
is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary
counter and has control inputs for enabling or disabling the clock (CP), for clearing the
counter to its maximum count and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count output (TC) are active-LOW
logic.
In normal operation, the counter is decremented by one count on each positive-going
transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is
HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is
LOW, and remains LOW for one full clock period.
When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7)
is clocked into the counter on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam
input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE,
TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its
maximum count (decimal 255) regardless of the state of any other input.
If all control inputs except TE are HIGH at the time of zero count, the counters will jump to
the maximum count, giving a counting sequence of 256 clock pulses long.
The 74HC40103 may be cascaded using the TE input and the TC output, in either a
synchronous or ripple mode.
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
2. Features
s
s
s
s
s
Cascadable
Synchronous or asynchronous preset
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Applications
s
s
s
s
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters.
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
f
max
C
I
C
PD
[1]
Parameter
Conditions
Min
-
-
-
Typ
30
32
3.5
24
Max
-
-
-
-
Unit
ns
MHz
pF
pF
propagation delay CP to TC C
L
= 15 pF;
V
CC
= 5 V
maximum clock frequency
input capacitance
power dissipation
capacitance
V
I
= GND to V
CC
[1]
C
L
= 15 pF;
V
CC
= 5 V
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
9397 750 13812
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
5. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC40103N
74HC40103D
74HC40103DB
74HC40103PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT38-4
SOT109-1
SOT338-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
6. Functional diagram
14
TC
1
9
3
P7 13
P6 12
P5 11
P4 10
P3 7
P2 6
1 CP
P1 5
P0 4
4
5
6
7
10
11
12
13
CP PL TE
P0
P1
P2
P3
P4
P5
P6
P7
PE
15
MR
2
001aab921
TC
14
PE PL TE MR
15
9
3
2
001aab923
Fig 1. Functional diagram
Fig 2. Logic symbol
9397 750 13812
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 25
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Product data sheet
Rev. 03 — 12 November 2004
to other 7
flip-flops
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13812
Philips Semiconductors
PE
PL
CP
MR
TC
P0
P1
P2
P3
P4
P5
P6
P7
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
J
MR
J
Q
CP
PL
PE
FF
1
CP
PL
PE
FF
2
CP
PL
PE
FF
3
CP
PL
PE
FF
4
CP
PL
PE
FF
5
CP
PL
PE
FF
6
CP
PL
PE
FF
7
CP
PL
PE
FF
8
TE
TE
TE
TE
TE
TE
TE
TE
8-bit synchronous binary down counter
TE
001aab924
74HC40103
5 of 25
Fig 5. Logic diagram
PCB设计
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