The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12611-6E
8-bit Microcontrollers
CMOS
F
2
MC-8FX MB95110M Series
MB95117M/F114MS/F114NS/F114JS/F116MS/F116NS/F116JS/F116MAS/F116NAS
MB95F118MS/F118NS/F118JS/F114MW/F114NW/F114JW/F116MAW/F116NAW
MB95F116MW/F116NW/F116JW/F118MW/F118NW/F118JW/FV100D-103
■
DESCRIPTION
The MB95110M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
■
FEATURES
•
F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
•
Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product, except MB95F116MAW/F116NAW)
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the
"Customer Design Review Supplement"
which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2006-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
MB95110M Series
(Continued)
•
Timer
• 8/16-bit compound timer
×
2 channels
Can be used to interval timer, PWC timer, PWM timer and input capture.
• 8/16-bit PPG
×
2 channels
• 16-bit PPG
×
1 channel
• Time-base timer
×
1 channel
• Watch prescaler (for dual clock product)
×
1 channel
•
LIN-UART
×
1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
•
UART/SIO
×
1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
2
C
×
1 channel
•
I
Built-in wake-up function
•
External interrupt
×
8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
•
8/10-bit A/D converter
×
8 channels
8-bit or 10-bit resolution can be selected
•
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Time-base timer mode
•
I/O port
• The number of maximum ports
- Single clock product : 39 ports
- Dual clock product : 37 ports
• Configuration
- General-purpose I/O ports (N-ch open drain) : 2 ports
- General-purpose I/O ports (CMOS)
: Single clock product : 37 ports
Dual clock product : 35 ports
•
Programmable input voltage levels of port
Automotive input level
/
CMOS input level
/
hysteresis input level
•
Dual operation Flash memory (Except MB95F116MAW/F116NAW/F116MAS/F116NAS)
Erase/Write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
•
Flash memory security function
Protects the content of Flash memory (Flash memory device only)
2
DS07-12611-6E
MB95110M Series
■
MEMORIY LINEUP
Flash memory
MB95F114MS/F114NS/F114JS
MB95F114MW/F114NW/F114JW
MB95F116MS/F116NS/F116JS/
MB95F116MAS/F116NAS
MB95F116MW/F116NW/F116JW/
MB95F116MAW/F116NAW
MB95F118MS/F118NS/F118JS
MB95F118MW/F118NW/F118JW
16 Kbytes
RAM
512 bytes
32 Kbytes
1 Kbyte
60 Kbytes
2 Kbytes
DS07-12611-6E
3
MB95110M Series
■
PRODUCT LINEUP
Part number
Parameter
MB95F114MS/ MB95F114NS/ MB95F114MW/
MB95F114NW/
MB95F116MS/ MB95F116NS/ MB95F116MW/
MB95F116NW/
MB95117M
MB95F116MAS/ MB95F116NAS/ MB95F116MAW/ MB95F116NAW/
MB95F118MS
MB95F118NS
MB95F118MW/
MB95F118NW
MB95F114JS/
MB95F116JS/
MB95F118JS
MB95F114JW/
MB95F116JW/
MB95F118JW
Type
ROM capacity*
1
RAM capacity*
1
Reset output
Clock system
Option*
2
MASK
ROM
product
48 Kbytes
Yes/No
Selectable
single/dual
clock*
3
Flash memory product
60 Kbytes (Max)
2 Kbytes
(
Max
)
Yes
Single clock
No
Yes
No
:
:
:
:
:
:
No
Dual clock
Yes
No
Single clock Dual clock
Yes
Yes
Low voltage
Yes / No
detection reset
Clock
supervisor
Yes / No
CPU functions
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
136
8 bits
1 to 3 bytes
1, 8, and 16 bits
61.5 ns (at machine clock frequency 16.25 MHz)
0.6
μs
(at machine clock frequency 16.25 MHz)
General
purpose
I/O ports
Time-base
timer
(1 channel)
Peripheral functions
Watchdog
timer
Wild register
•
Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
•
Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
Programmable input voltage levels of port :
Automotive input level
/
CMOS input level
/
hysteresis input level
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
(Continued)
I
2
C
(1 channel)
UART/SIO
(1 channel)
4
DS07-12611-6E
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
