MIC4123/4124/4125
Micrel, Inc.
MIC4123/4124/4125
Dual 3A-Peak Low-Side MOSFET Driver
Bipolar/CMOS/DMOS Process
General Description
The MIC4123/4124/4125 family are highly reliable BiC-
MOS/DMOS buffer/driver/MOSFET drivers. They are higher
output current versions of the MIC4126/4127/4128, which
are improved versions of the MIC4426/4427/4428. All three
families are pin-compatible. The MIC4123/4124/4125 driv-
ers are capable of giving reliable service in more demanding
electrical environments than their predecessors. They will
not latch under any conditions within their power and voltage
ratings. They can survive up to 5V of noise spiking, of either
polarity, on the ground pin. They can accept, without either
damage or logic upset, up to half an amp of reverse current
(either polarity) forced back into their outputs.
The MIC4123/4124/4125 series drivers are easier to use, more
flexible in operation, and more forgiving than other CMOS
or bipolar drivers currently available. Their BiCMOS/DMOS
construction dissipates minimum power and provides rail-to-
rail voltage swings.
Primarily intended for driving power MOSFETs, the
MIC4123/4124/4125 drivers are suitable for driving other loads
(capacitive, resistive, or inductive) which require low-imped-
ance, high peak currents, and fast switching times. Heavily
loaded clock lines, coaxial cables, or piezoelectric transducers
are some examples. The only known limitation on loading is
that total power dissipated in the driver must be kept within
the maximum power dissipation limits of the package.
Features
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Reliable, low-power bipolar/CMOS/DMOS construction
Latch-up protected to >200mA reverse current
Logic input withstands swing to –5V
High 3A-peak output current
Wide 4.5V to 20V operating range
Drives 1800pF capacitance in 25ns
Short <50ns typical delay time
Delay times consistent with in supply voltage change
Matched rise and fall times
TTL logic input independent of supply voltage
Low equivalent 6pF input capacitance
Low supply current
3.5mA with logic-1 input
350µA with logic-0 input
Low 2.3Ω typical output impedance
Output voltage swings within 25mV of ground or V
S
.
‘426/7/8-, ‘1426/7/8-, ‘4426/7/8-compatible pinout
Inverting, noninverting, and differential configurations
Exposed backside pad packaging reduces heat
ePAD SOIC-8L (θ
JA
= 58°C/W)
4mm x 4mm MLF™-8L (θ
JA
= 45°C/W)
Functional Diagram
V
S
0.6mA
0.1mA
INV ERT ING
Integrated Component Count:
4 Resistors
4 Capacitors
52 Transistors
OUTA
INA
2kΩ
NONINV ERTING
0.6mA
0.1mA
INV ERT ING
OU TB
INB
2kΩ
NONINV ERTING
GND
Ground Unused Inputs
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2005
1
M9999-052405
MIC4123/4124/4125
Micrel, Inc.
Absolute Maximum Ratings
(Note 1)
Supply Voltage ........................................................... +24V
Input Voltage .................................. V
S
+ 0.3V to GND – 5V
Junction Temperature ................................................150°C
Storage Temperature Range ......................–65°C to 150°C
Lead Temperature (10 sec.) ......................................300°C
ESD Susceptability,
Note 3
Operating Ratings
(Note 2)
Supply Voltage (V
S
) ......................................+4.5V to +20V
Junction Temperature Range .....................–40°C to 125°C
Package Thermal Resistance
4mm X 4mm MLF
θ
JA
......................................... 45°C/W
EPAD SOIC-8L
θ
JA
............................................. 58°C/W
MIC4123/4124/4125 Electrical Characteristics
(Note 4)
4.5V ≤ V
S
≤ 20V; T
A
= 25°C,
bold
values indicate –40°C ≤ T
J
≤ +125°C; unless noted. Input Voltage slew rate >2.5V/µs.
Symbol
Input
V
IH
V
IL
I
IN
Output
V
OH
V
OL
R
O
High Output Voltage
Low Output Voltage
Output Resistance HI State
Output Resistance LO State
I
PK
I
Peak Output Current
Latch-Up Protection
Withstand Reverse Current
Rise Time
Fall Time
Delay Tlme
Delay Time
test Figure 1, C
L
= 1800pF
test Figure 1, C
L
= 1800pF
test Ffigure 1, C
L
= 1800pF
test Figure 1, C
L
= 1800pF
>200
I
OUT
= 100µA
I
OUT
= –100µA
I
OUT
= 10mA, V
S
= 20V
I
OUT
= 10mA, V
S
= 20V
V
S
–0.025
2.3
2.2
3
V
0.025
5
8
5
8
V
Ω
Ω
Ω
Ω
A
mA
Logic 1 Input Voltage
Logic 0 Input Voltage
Input Current
0V ≤ V
IN
≤ V
S
–1
–10
2.4
1.5
1.3
0.8
1
10
V
V
µA
µA
Parameter
Conditions
Min
Typ
Max
Units
Switching Time
t
R
t
F
t
D1
t
D2
Power Supply
I
S
I
S
Note 1.
Note 2.
Note 3.
Note 4.
11
11
44
59
35
60
35
60
75
100
75
100
2.5
3.5
0.25
0.3
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
Power Supply Current
Power Supply Current
V
IN
= 3.0V (both inputs)
V
IN
= 0.0V (both inputs)
1.5
0.15
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Devices are ESD sensitive. Handling precautions recommended. ESD tested to human body model, 1.5k in series with 100pF.
Specification for packaged product only.
May 2005
3
M9999-052405
FPGA/CPLD
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