IDT74ALVCH16525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
REGISTERED BUS TRANS-
CEIVER WITH 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH16525:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
–
IDT74ALVCH16525
DESCRIPTION:
This 18-bit registered bus transceiver is built using advanced dual
metal CMOS technology. Data flow in each direction is controlled by
output-enable (OEAB and OEBA) and clock-enable (CLKENAB and
CLKENBA) inputs. For the A-to-B data flow, the data flows through a
single register. The B-to-A data can flow through a four-stage pipeline
register path, or through a single register path, depending on the state
of the select (SEL) input. Data is stored in the internal registers on the low-
to-high transition of the clock (CLK) input, provided that the appropriate
CLKEN inputs are low. The A-to-B data transfer is synchronized to the
CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA
and CLK2BA inputs.
The ALVCH16525 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCH16525 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
Functional Block Diagram
CLKAB
55
CLK1BA
30
CLK 2BA
29
CLKENBA
28
CLKE NAB
1
OEAB
2
OEBA
27
56
SEL
CE
0
C1
A
1
3
1D
C1
1
1D
C1
1D
C1
1D
54
CE
CE
CE
B
1
CE
C1
1D
1 of 18 Channels
To 17 Other C hannels
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4694/1
IDT74ALVCH16525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
CLKENAB
OEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
CLKENBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
56
55
54
53
52
51
50
49
48
47
46
45
SEL
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLK1BA
CLK2BA
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
NOTE:
1. As applicable to the device type.
SSOP/TSSOP/TVSOP
TOP VIEW
2
IDT74ALVCH16525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names
Description
CLKAB
Clock Input for the A to B direction
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
Ax
Bx
Clock Input for the B to A pipeline register
Clock Input for the B to A output register
Clock Enable for the CLK1BA and CLK2BA clocks (Active LOW)
Clock Enable for the CLKAB clock (Active LOW)
Output Enable for the B port (Active LOW)
Output Enable for the A port (Active LOW)
Select pin for pipelined/non-pipelined mode in
the B-to-A direction (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
(1)
FUNCTION TABLES
Inputs
CLKENAB
H
L
L
CLKAB
X
↑
↑
(1)
A-TO-B STORAGE (OEAB = L, OEBA = H)
Output
Ax
X
L
H
Bx
B
0(2)
L
H
B-TO-A STORAGE (OEBA = L, OEAB = H)
Inputs
CLKENBA
H
L
L
L
L
CLK2BA
X
↑
↑
↑
↑
CLK1BA
X
X
X
↑
↑
SEL
X
H
H
L
L
Bx
X
L
H
L
H
Output
Ax
A
0(2)
L
H
L
(3)
H
(3)
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were es-
tablished.
3. Three CLK1BA edges are one CLK2BA needed to propagate data from B
to A when SEL is low.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
4
IDT74ALVCH16525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
—
V
CC
= 3.3V ± 0.3V
Typical
160
160
Unit
pF
pF
SWITCHING CHARACTERISTICS
Symbol
Parameter
(1)
V
CC
= 2.5V ± 0.2V
Min.
Max.
V
CC
= 2.7V
Min.
Max.
V
CC
= 3.3V ± 0.3V
Min.
Max.
Unit
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
SU
t
SU
t
SU
t
SU
t
SU
t
SU
t
H
t
H
t
H
t
H
t
H
t
H
t
H
t
W
t
SK
(o)
Propagation Delay
CLKAB to Bx or CLK2BA to Ax
Output Enable Time
OEAB to Bx or OEBA to Ax
Output Disable Time
OEAB to Bx or OEBA to Ax
Setup Time, Ax data before CLKAB↑
Setup Time, Bx data before CLK2BA↑
Setup Time, Bx data before CLK1BA↑
Setup Time, SEL before CLK2BA↑
Setup Time, CLKENAB before CLKAB↑
Setup Time, CLKENBA before CLK1BA↑
Setup Time, CLKENBA before CLK2BA↑
Hold Time, Ax data after CLKAB↑
Hold Time, Bx data after CLK2BA↑
Hold Time, Bx data after CLK1BA↑
Hold Time, SEL after CLK2BA↑
Hold Time, CLKENAB after CLKAB↑
Hold Time, CLKENBA after CLK1BA↑
Hold Time, CLKENBA after CLK2BA↑
Pulse Duration, CLK HIGH or LOW
Output Skew
(2)
120
1
1
1
1.3
2.1
1.3
3.3
2.1
2.7
2.7
0.7
0.4
0.8
0
0.1
0
0
3.2
—
—
4.5
6.1
6.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
125
—
—
—
1.3
1.8
1.2
3.3
1.9
2.5
2.5
0.4
0
0.4
0
0.3
0
0
3.2
—
—
4.4
6.1
5.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
1
1
1
1.3
1.7
1.1
3.3
1.6
2.1
2.2
0.9
0.6
1
0.1
0.3
0.1
0
3
—
—
4.2
5.1
4.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
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