QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FEATURES:
−
−
10 output, low skew signal buffer
Guaranteed low skew:
•
0.7ns output skew (same bank)
•
0.9ns output skew (different bank)
•
1ns part-to-part skew
25Ω on-chip resistors available for low noise
Input hysteresis for better noise margin
Monitor output
Undershoot clamp diodes on all inputs
Std. and A speed grades
Available in QSOP and SOIC packages
QS52805T/AT
ADVANCE
INFORMATION
DESCRIPTION
The QS52805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS52805T has on-chip series termination resistors for lower noise
clock signals. The QS52805T series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise sensitive
clock distribution circuits. These clock buffer products are designed for use
in high-performance workstations and in embedded and personal comput-
ing systems. Several devices can be used in parallel or scattered throughout
a system for guaranteed low skew, system-wide clock distribution networks.
The QS52805T is characterized for operation at -40°C to +85°C.
−
−
−
−
−
−
FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
5
OA
1
MON
5
IN
B
OB
5
OB
1
OE
B
NOTE:
This device has 25Ω series termination resistors on each clock output including monitor.
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
AUGUST 2000
DSC-5480/-
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
CC A
OA
1
OA
2
OA
3
G ND
A
OA
4
OA
5
G N DQ
O E
A
IN
A
1
2
3
4
5
6
7
8
9
10
SO20-2
SO20-8
20
19
18
17
16
15
14
13
12
11
V
CC B
OB
1
OB
2
OB
3
G ND
B
OB
4
OB
5
MON
O E
B
IN
B
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
V
AC
I
OUT
T
STG
T
J
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Input Voltage V
IN
AC Input Voltage (pulse width
≤20ns)
DC Input Diode Current V
IN
< 0
DC Output Current Max. Sink Current/Pin
Storage Temperature
Junction Temperature
(1)
Unit
V
V
V
V
mA
mA
°C
°C
Max.
– 0.5 to +7
– 0.5 to +7
– 0.5 to +7
-3
-20
120
– 65 to +150
150
QSOP/ SOIC
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
Pins
C
IN
C
OUT
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V)
Max.
(1)
6
9
Unit
pF
pF
Typ.
4
7
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
OEA, OEB
INA, INB
OAn, OBn
MON
I/O
I
I
O
O
Description
Output Enable Inputs
Clock Inputs
Clock Outputs
Unbuffered Monitor Output
2
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
Symbol
V
IH
V
IL
V
IC
V
OH
V
OL
I
IN
I
OFF
I
OZ
I
OS
∆V
T
R
OUT
Parameter
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage
(3)
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Input/Output Power Off Leakage
Output Leakage Current
Short Circuit Current
Input Hysteresis
Output Resistance
(2,3)
Test Conditions
Guaranteed Logic HIGH for All Inputs
Guaranteed Logic LOW for All Inputs
Vcc = Min., I
IN
= -18mA
Vcc = Min., I
OH
= -12mA
Vcc = Min., I
OL
= 12mA
Vcc = Max., V
IN
= Vcc or GND
Vcc = 0V, V
IN
or V
OUT
= Vcc or GND
Vcc = Max., V
OUT
= Vcc or GND
Vcc = Max., V
OUT
= GND
V
TLH
- V
THL
for All Inputs
Vcc = Min., I
OL
= 12mA
Min.
2
—
—
2.4
—
—
—
—
Typ.
(1)
—
—
–0.7
—
—
—
—
—
—
0.2
28
Max.
—
0.8
–1.2
—
0.5
±1
±1
±1
–250
—
—
Unit
V
V
V
V
V
µA
µA
µA
mA
V
Ω
–
60
—
—
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
∆I
CC
I
CCD
I
C
Parameter
Quiescent Power Supply Current
Supply Current per Input HIGH
Dynamic Power Supply Current per Output
(2)
Total Power Supply Current Examples
(2,4)
Test Conditions
(1)
V
CC
= Max., V
IN
= GND or Vcc
V
CC
= Max., V
IN
= 3.4V, f
I
= 0MHz
V
CC
= Max., V
IN
= GND or Vcc
Outputs Enabled, 50% duty cycle
V
CC
= Max.,
OEA
=
OEB
= GND
50% duty cycle, f
I
= 10MHz
Five outputs toggling
Unused inputs = GND or Vcc
V
CC
= Max.,
OEA
=
OEB
= GND
50% duty cycle, f
I
= 2.5MHz
All outputs toggling
Typ.
(3)
0.005
1
0.08
V
IN
= GND or Vcc
V
IN
= GND or 3.4V
6.6
7.2
Max.
0.5
2.5
0.18
9.5
10.8
Unit
mA
mA
mA/MHz
mA
V
IN
= GND or Vcc
V
IN
= GND or 3.4V
4.3
5.6
5.5
8
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 5.0V, T
A
= 25°C.
4. I
C
= I
CC
+ (∆I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
T
= Number of TTL HIGH inputs at D
H
(one or two)
f
O
= Output Frequency
N
O
= Number of outputs at f
O
3
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF (no resistor)
QS52805T
Symbol
t
SK(01)
t
SK(02)
t
SK(P)
t
SK(T)
Parameter
(1)
Skew between two outputs, same transition, same bank
Skew between two outputs, same transition, different banks
Pulse Skew; opposite transition skew, same output (t
PHL
- t
PLH
)
Part-to-part skew
(2)
Min.
—
—
—
—
Max.
0.7
0.9
1
1.5
Min.
—
—
—
—
QS52805AT
Max.
0.7
0.9
1
1
Unit
ns
ns
ns
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not tested. Skew parameters apply to propagation delays only.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF (no resistor)
QS52805T
Symbol
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
R
t
F
Parameter
(1)
Propagation Delay
(2)
Output Enable Time
Output Disable Time
Output Rise Time, 0.8V to 2V
(3)
Output Fall Time, 2V to 0.8V
(3)
Min.
1.5
1.5
1.5
—
—
Max.
6.5
8
7
1.5
1.5
Min.
1.5
1.5
1.5
—
—
QS52805AT
Max.
5.8
8
7
1.5
1.5
Unit
ns
ns
ns
ns
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not tested.
4
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter
Tested
Switch
Position
t
PLZ
, t
PZL
All Others
V
CC
V
IN
Pulse
Generator
50
Ω
DUT
50pF
500
Ω
V
OUT
500
Ω
Closed
Open
6.0 V
Pulse generator for all pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
PROPAGATION DELAY
3V
INPUT
t
PLH
t
PHL
V
OH
2.0V
1.5V
0.8V
V
OL
t
R
t
F
1.5V
0V
INPUT
PULSE SKEW — t
SK(P)
3V
1.5V
0V
t
PLH
OUTPUT
t
PHL
V
OH
1.5V
V
OL
t
SK(p)
= t
PHL
- t
PLH
OUTPUT
OUTPUT SKEW (SAME BANK) — t
SK(O1)
3V
INPUT
t
PLH1
t
PHL1
V
OH
OUTPUT 1
1.5V
V
OL
t
SK(01)
OUTPUT 2
t
SK(01)
V
OH
1.5V
V
OL
t
PLH2
t
PHL2
1.5V
0V
INPUT
OUPUT SKEW (DIFFERENT BANKS) — t
SK(O2)
3V
1.5V
0V
t
PLHA
t
PHLA
V
OH
OUTPUT A
1.5V
V
OL
t
SK(02)
OUTPUT B
t
SK(02)
V
OH
1.5V
V
OL
t
PLHB
t
PHLB
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
t
PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
t
PLZ
3V
1.5V
0.3V V
OL
t
PHZ
0.3V V
OH
PART 2 OUTPUT
PART 1 OUTPUT
DISABLE
3V
1.5V
0V
INPUT
PART-TO-PART SKEW — t
SK(T)
3V
1.5V
0V
t
PLH1
t
PHL1
V
OH
1.5V
V
OL
t
SK(t)
t
SK(t)
V
OH
1.5V
V
OL
t
PLH2
t
PHL2
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
