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SI4123G-BT

产品描述RF and Baseband Circuit, PDSO24, TSSOP-24
产品类别模拟混合信号IC    信号电路   
文件大小702KB,共32页
制造商Silicon Laboratories Inc
下载文档 详细参数 全文预览

SI4123G-BT概述

RF and Baseband Circuit, PDSO24, TSSOP-24

SI4123G-BT规格参数

参数名称属性值
厂商名称Silicon Laboratories Inc
零件包装代码TSSOP
包装说明TSSOP,
针数24
Reach Compliance Codeunknown
模拟集成电路 - 其他类型PHASE LOCKED LOOP
JESD-30 代码R-PDSO-G24
长度7.8 mm
功能数量1
端子数量24
最高工作温度85 °C
最低工作温度-20 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3 V
表面贴装YES
温度等级OTHER
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
宽度4.4 mm

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Si4133G
Si4123G/22G/13G/12G
D
UAL
-B
AND
RF S
YNTHESIZER
W
ITH
I
NTEGRATED
VCO
S
F
OR
GSM
AND
GPRS W
IRELESS
C
OMMUNICATIONS
Features
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
33
S
i4
1
G
-B
T
Dual-band RF Synthesizers
IF synthesizer: 500 to
1000 MHz
Integrated VCOs, loop filters,
varactors, and resonators
Minimal number of external
components required
Fast settling time: 140
µs
GPRS Class 12 compliant
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP and
28-pin MLP
Ordering Information:
See page 28.
Applications
GSM 850, E-GSM 900, DCS 1800, and PCS 1900 cellular
telephones
GPRS data terminals
HSCSD data terminals
Pin Assignments
Si4133G-BT
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
Description
The Si4133G is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. The Si4133G includes three VCOs, loop filters, reference
and VCO dividers, and phase detectors. Divider and powerdown settings
are programmable with a three-wire serial interface.
Functional Block Diagram
Reference
Amplifier
Power
Down
Control
GNDR
RFOUT
VDDR
XIN
÷
65
Phase
Detector
RF1
RFLA
RFLB
PWDN
SDATA
IFOUT
23
GNDR
SCLK
SDATA
SCLK
SEN
Serial
Interface
22-bit
Data
Register
Phase
Detector
RF2
RFLC
RFLD
GNDR
RFLD
RFLC
1
2
3
4
5
6
7
28
27
26
25
24
22
21
20
19
GNDI
SEN
VDDI
÷
N
Si4133G-BM
RFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
÷
N
Phase
Detector
IF
IFOUT
IFLA
IFLB
AUXOUT
Test
Mux
GNDR
RFLB
RFLA
GNDR
GND
Pad
18
17
16
15
÷
N
8
9
10
11
12
13
14
RFOUT
AUXOUT
GNDR
GNDR
Patents pending
Rev. 1.4 5/03
Copyright © 2003 by Silicon Laboratories
Si4133G-DS14
PWDN
GNDD
VDDR

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